Dear all,
Can anyone help me to place pins with limited number of layers? I trust the placement of Encounter so I don't want to
go for pin editor. I just want to limit layers, e.g up to M4. By default pins are placed to all the layers available in LEF
Thanks,
Aram
If there are some undriven signals in my design,can RTL-Compiler find that?
Is there any synthesis "warning", "Info" or "Error about this issue?
Should I set any attribure to find this problem?
Here are some sample code:
module mydesign (A, B) ;
input [3:0] A;
output [3:0] B;
wire [1:0] undriven_signal;
reg [5:0] reg_A;
always@(*) begin
case(A)
4'd0: XXXXXX
4'd1: XXXXXX
4'd2: XXXXXX
4'd3: XXXXXX
4'd4: XXXXXX
4'd5: XXXXXX
4'd6: XXXXXX
4'd7: XXXXXX
4'd8: XXXXXX
4'd9: XXXXXX
4'd10: XXXXXX
4'd11: XXXXXX
4'd12: XXXXXX
4'd13: XXXXXX
4'd14: XXXXXX
4'd15: reg_A = {undriven_signal, A};
end
endmodule
Warning : Undriven signal detected. [ELABUTL-125]
This warning only tell me that reg_A has some undriven signals, but I want the tool tells me more about undriven_signal.
The tool tells me that the warning location at line "case(A)". Can the tool find the line at "4'd15: reg_A = {undriven_signal, A};"?
Dear Friends,
I have a block with the same structure (sub module) repeating many times. I have done manual placement & routing for one slice
and saved a design.
Now I need to instantiate and use a hand made slice many times (just like instantiating in layout editor)
Any ideas how I can do that?
Thanks in Advance,
Aram
We
created ClocktreeSpec(UpdatedClock2.ctstch) tool itself is adding extra
string to the file name ".functional" and unable to synthesize the
clock tree, stating the following error
**ERROR: (ENCSYUTIL-96): Cannot open (for read) Clock Synthesis Technology File file: "UpdatedClock2.ctstch.functional".
Reason for error: No such file or directory.
**ERROR: (ENCCK-430): CTS was unable to open the file UpdatedClock2.ctstch.functional.
How to overcome this?
Hi everyone,
I have couple of doubts. Please help me out.
1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for it??
2.How to define virtual clock for my combinational design module??
Thanks in advance :)
Hi, I read somewhere that it is a good paractice w.r.t elctromigration to have 45 degree bend in routing. How to do that in encounter?
-Arslan.
Hi, Which data is used by nano router from timing lib while performing current driven routing ? and what type of data is used by optimizer while performing SI optimizations, if I dont provide .cdb files.?
How to get all multidriven net ??in less runtime......
Thanks in advance
Hello people!
I am trying to do floor planning for my design for the first time. Actually I have done the basic fllorplanning and have placed the i/o pads as well but not the macro cells ( placement in the core area) yet. I verified the geometry after this step and found a lot of spacing violations and short violations at the corner pads. I corrected the spacing violations by adjusting the die size of the floorplan. But now I have the short violations ( All the spacing violations also got converted to short violations). Can anyone please tell me how I can correct those. I have attached a snap shot.
Thank you
Hi All, I have a couple of questions on running SOC Encounter. My goal is to run the encounter using a tcl script and be able to have a flow that runs through all the necessary steps by running the script, instead of having to use the GUI.
1. Does anybody know a good way (or if it is even possible) to automate the timing optimization process in SOC Encounter using tcl script? Currently, it looks like you have to run optDesign command for setup/hold/DRV optimization and if the violations are not fixed the first time around, you have to run optDesign command multiple times until timing is met. Is there a good way of using the tcl script to do this automatically? For instance is it possible to have encounter run the timing optimizations automatically through tcl scripts until all the timing and DRV violations are fixed?
2. Also, is it possible to have Encounter skip the optimization process if the timing slacks meet the target? The way Encounter works now (for me anyway) is that if I run optDesign command the tool will perform optimization even if the design currently meets all timing/DRV constraints. When running optDesign, is it possible to have Encounter check the timing constraints and skip optDesign process if the constraints are met?
Thanks!!
Hi All ,
In a inclkSrc2reg path group i am seeing Source Insertion Delay<value> in calculation of Beginpoint Arrival Tim.
how tool find out this source insertion delay?
Thanks in advance.
see title
Hello,
I'm having problems with adding/naming Vias. I select the "Add via", then "by geometry", specify it's geometry and put (click) it over an existing net. The problem however is, that the Via isn't connected to the net. The attribute window says it's net is _NULL.
I acquired the property value with:
>dbGet selected.net.name
and it returned _NULL as expected, however the counterpart command
>dbSet selected.net.name desired_name
returned "Attribute 'name' of object 'net' does not have set permission .....", which makes sense, sinse the attribute window didn't allow the change either.
The question therefore is how to tell a VIA that it belongs to a particular net, apart by crossing nets orthogonally?
regards
Hello,
I donot have much Experience in Place and route operation. The problem is that I have completed the place and routing of the core area as well as the IO pads. When I run DRC verify geometry I have no violations in the core area but in the Corner IO pads I get two short erros ( LeftBottom and Top right corner pads) in the dummy cell pins. It looks strange because even other two corners have the same dummy Pins but there are no short errors. The two Violations I am getting are
SHORT: Pin of Cell io_pad_left_bottom_corner & Blockage of Cell fillperi_S_0 ( M3 )
Bounds : ( 112.000, 1.900 ) ( 112.000, 2.100 )
SHORT: Pin of Cell io_pad_right_top_corner & Blockage of Cell fillperi_N_78 ( M3 )
Bounds : ( 1568.200, 1503.300 ) ( 1568.200, 1503.500 )
Can anyone please advise me on how to fix it.?
Hallo,
I am creating a standard cell library. Should I generate Netlist including the load caps the schematic. if at all does it make any difference, including and ignoring load cas in Netlist used in Library generation.
Dear sir/madam,
i am now using cadence encounter (EDI) 11.1. in the IMPORT Design i am now select the netlist file and also apply the mmmc config file, and i was also apply power nets and lef (all.lef) files. finally i will click ok the tool shows the error
ERROR (ENCVL-902): Failed to read Netlist filename.v please give me the solutions for this problem
THANKS & REGARDS,
M.Muthukumar.
Hello,
I am a newbie at placement and routing. I want the routing to be done using only metal 3,4 and 5 ( basically other than metal 1 and 2).
Can anyone please advise me as to where I have to mention this and the command used to get routing metal layers set?
Any help in this regard is appreciated!
Thank you
Good afternoon everybody,
I'm trying to find a way to add space between all of my cells when they are placed using Encounter. The process I'm working out of only has one metal layer, so I need to leave plenty of room for routing with M1 and poly bridges only. I have found Cell, Instance, and Module Padding in the documentation, but they do not seem to work reliably. Perhaps I am configuring it incorrectly? It seems that no matter how I tweak the settings, I still get 5-10% of the cells abutted together, with plenty of spare space in the floorplan for them to spread out. Any ideas?
Thanks!
