in VSVN netlist getting error , i am using mlcv swicth
Hi,I am running mlcv switch in VSVN netlist, Ia m doing in batch mode, for single lib,cell,view i am not getting error, for mlcv only i am getting this , this is a new feature from cadencethe error is...
View ArticleCadence Genus: Submodule synthesis and reuse and integrate it in top module
I'm currently working on a large RTL design using Cadence Genus, and I'm running into some issues with hieratical synthesis and submodule resue. My goal is to synthesize submodules independently, save...
View ArticleSynthesizing Specific Gates in Cadence Genus
Hello Cadence Community,I'm working on a flattened netlist in Cadence Genus for a design and would like to apply targeted synthesis optimizations to a specific list of gates (e.g., g1234, g5678) while...
View ArticleTracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus
Hi Cadence Community,I'm using Genus 21 to synthesize a design and need help with two goals:Tracing gates to RTL lines: I've set set_attribute hdl_track_filename_row_col true, which enables RTL source...
View ArticleINNOVUS: connect internal power nets between hard macros
I have a design with two hard macros, where one of the macros creates internal supply voltages for the other. In the synthesized netlist, the respective pins (e.g. VQQ) are connected to common nets. In...
View ArticleFoundation flow stylus
Hi Guys,I am new to entire cadenced tool set,working for a project where i have to primarily use foundation flow scripts to construct basic flow for rtl to gds.I have explored on...
View ArticleCongestion at Routing Stage
I'm seeing congestion at the routing stage. I'd truly appreciate it if someone could guide me on what my approach should be and which things I should take care of to address this congestion issue at...
View ArticleMin Pulse Width Violation
How do we address if there is a Minimum Pulse Width violation in the design?
View ArticleHow to manage block-level and top-level SDC constraints?
I am currently facing some issues trying perform a hierarchical implementation of a chip with Cadence tools, particularly on how to manage timing constraints. The chip includes a few digital blocks...
View ArticleDRC Violations due to Macro Placement and Power Straps in Innovus Stylus Flow
I have a working Genus + Innovus Stylus 21.1 for a design. But now, instead of flattening everything, I need to turn one of the modules into a macro and place it in my top level.I limit macro's top...
View ArticleResidual power in whole design vs summed gate groups in Joules, even with...
Hi everyone,I'm running power analysis in Joules (Version v21.19) using simulation-based activity from a VCD file for a purely combinational design (ISCAS-85 c432). To understand the power contribution...
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Issue about using SkyWater130 and Genus
Hey all,I am trying to synthesize a design using Cadence Genus with SkyWater 130. Although the synthesis does not report any issue, when I try to simulate the gate-level netlist using XCELIUM, it gives...
View Articlegsclib045 data sheet available?
While we were able to obtain all the required implementation views and reference manual for the gsclib045 example stdcell library, I was unable to find a data sheet that explains the individual cells....
View ArticleaddRing creating rings outside design boundary
It seems that there is a glitch involved with creating the power ring.I set the floorplan with floorPlan -d $TOP_macro_sizex $TOP_macro_sizey 0.612 0.612 0.612 0.612 -noSnapToGridThis sets the core and...
View ArticleTiming Differences seen between Innovus & Tempus
Hi Experts ,I see the following timing differences between Tempus & Innovus . The path which is matching in Innovus but failing in Tempus .Pasting the headers of both the reports :Tempus : Failing...
View ArticleHow to create tech file (.tch) and captable file (.capTl) if we have .ict...
I am trying to learn the implementation of a Digital design. I am following Cadence-RLT-to-GDSII course. But I am using my own pdk which is TSMC 65nm. I am unable to file the Tech files and Captable...
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ecoChangeCell
Hi, I’m new to using Innovus and I’m trying to rename a submodule called “abc” to a new submodule "abc2" with the same ports in a netlist. The structure looks like this: top/u_abc. I need to change the...
View Article".tch" file for QRC extraction of RC corners in MMMC.VIEW file.
Greetings of the day !I have designed an SPI ( Serial Peripheral Interface) Module using TSMC65nm technology in Cadence Innovus. At last during the Sign-Off stage I am checking for Slack values...
View ArticleSkewing of sink pins at post route
Hi , In my design, the clock tree looks good up to the routing stage, and I want the tool to preserve it as-is. However, during the post-route optimization phase using:opt_design -post_route...
View Article"Undefined scan chain" error during Innovus `place`
I'm trying to run a RocketChip (rv64gc) design through the Genus/Innovus synth+place&route flow (with gpdk045 as the underlying technology), and running into a "scan chain" related issue during...
View ArticleProcedure in Innovus common UI to generate scripts for placement
In an older Innovus version (152), the following lines were executed before placement. pnrflow/ was generated in innovus using "writeFlowTemplate -directory pnrflow"./pnrflow/SCRIPTS/gen_flow.tcl...
View ArticlePower and Net Area Discrepancies in Joules When Analyzing PR Netlists Across...
Dear Cadence Community,Recently, our company upgraded Joules from version 22.17 to 23.14. While performing power analysis on the final place-and-route (PR) netlist of a project, I noticed a significant...
View Articleinnovus create offgrid viacuts
when using innovus, it sometimes create viacuts that are offgridthe vias themselves are on-grid but the metal around the vias is sometimes offgrid (e.g. it has 0.001um offgrid placements, while the...
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Issue while performing signoffTimeDesign in Innovus
Hello everyone,I am facing an Issue while executing signoffTimeDesign in Innovus . Once I invoke innovus tool, and run the below commands it works fine.But , after I source my design and then do...
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