Hi,
I hope this question is more relevant to this forum than Custom IC. I am trying to perform transistor level post layout simulation on a 'P&R'ed digital design. After P&R and timing optimizations, I import the post layout netlist (without physical only cells) to Virtuoso along with extracted .dspf file. I have the OA version of the reference standard cell library in Virtuoso in which all cell views have power and well contacts. However the .dspf from Innovus does not have these contacts in "instance" section, so that when the .dspf is annotated to the schematic netlist, spectre simulation stops throwing following error :
ERROR (SFE-45): `Xpipe_in_0__dxin': An instance of `DFQBRM1RA' needs at least 8 terminals (but has only 4).
The schematic Netlist looks like below:
subckt ND2M1R Z A B VDD VSS VBN VBP
M0 (N_8_M0_d B VSS VBN) n_12_llrvt l=6E-08 w=3E-07 sa=1.75E-07 \
sb=3.95E-07 nf=1 mis_flag=1 sd=200n as=5.25E-14 ad=2.4E-14 \
ps=9.5E-07 pd=4.6E-07 sca=21.1826 scb=0.0232952 scc=0.00281296 m=1 \
mf=1
M1 (Z A N_8_M0_d VBN) n_12_llrvt l=6E-08 w=3E-07 sa=3.95E-07 \
sb=1.75E-07 nf=1 mis_flag=1 sd=200n as=2.4E-14 ad=5.25E-14 \
ps=4.6E-07 pd=9.5E-07 sca=21.1826 scb=0.0232952 scc=0.00281296 m=1 \
mf=1
M2 (VDD B Z VBP) p_12_llrvt l=6E-08 w=4.5E-07 sa=1.75E-07 sb=4.35E-07 \
nf=1 mis_flag=1 sd=200n as=7.875E-14 ad=4.5E-14 ps=1.25E-06 \
pd=6.5E-07 sca=57.4294 scb=0.0457325 scc=0.00629633 m=1 mf=1
M3 (Z A VDD VBP) p_12_llrvt l=6E-08 w=4.5E-07 sa=4.35E-07 sb=1.75E-07 \
nf=1 mis_flag=1 sd=200n as=4.5E-14 ad=7.875E-14 ps=6.5E-07 \
pd=1.25E-06 sca=53.2271 scb=0.0383044 scc=0.00577594 m=1 mf=1
x_PM_ND2M1R\%B (B) _sub6
x_PM_ND2M1R\%A (A) _sub7
x_PM_ND2M1R\%VSS (VSS) _sub8
x_PM_ND2M1R\%Z (Z) _sub9
x_PM_ND2M1R\%VDD (VDD) _sub10
x_PM_ND2M1R\%VBN (VBN) _sub11
x_PM_ND2M1R\%VBP (VBP) _sub12
x_PM_ND2M1R\%8 (N_8_M0_d) _sub13
ends ND2M1R
whereas .dspf :
Xtest\/cla1\/U27 test\/cla1\/U27:A test\/cla1\/U27:B test\/cla1\/U27:Z ND2M1R
Is possible to include these pins when .dspf is extracted ? Or is there a workaround to bypass this in Virtuoso ?
My extraction settings in Innovus look like this :
setExtractRCMode -engine postRoute -effortLevel high
extractRC
mkdir TC/
rcOut -setload TC/${DESIGN_NAME}_tc.setload -rc_corner rc_tc
rcOut -setres TC/${DESIGN_NAME}_tc.setres -rc_corner rc_tc
rcOut -spf TC/${DESIGN_NAME}_tc.spf -rc_corner rc_tc
rcOut -spef TC/${DESIGN_NAME}t_tc.spef -rc_corner rc_tc
write_sdf -view data_gen_tc TC/${DESIGN_NAME}_tc.sdf
Thanks in advance
Anuradha