Hi all!
I'm trying to split a design during synthesis in order to implement a recurring subpart only one and then re-use it in cloned partitions in Innovus.
After searching the support site, I could solve the first problem: Extracting the subdesign.
My toplevel design is ControlBlock, which contains several (later hundreds) of instances of DoubleColumn.
set_db init_power_net VDD
set_db init_ground_net GND
::read_hdl -sv {
[…]
}
read_mmmc full.mmmc
read_physical -oa_ref_libs { … }
elaborate ControlBlock
set_db [get_db modules DoubleColumn*] .boundary_opto strict_no
init_design
create_derived_design {hinst:ControlBlock/gen_dcol[0].dc_I}
vcd design:DoubleColumn
syn_generic
syn_map
set_db write_sv_port_wrapper true
# write all formats that I can think of, to find one I can work with
write_design -innovus -hierarchical -base_name designs/DoubleColumn
write_db -common dbs/DoubleColumn
generate_ilm -basename ilms/DoubleColumn
At this stage, the proposed solution¹ changes back to the top design and performs synthesis there:
vcd set_db design:DoubleColumn .preserve true change_link -retain_exceptions -instances {hinst:ControlBlock/gen_dcol[0].dc_I} {hinst:ControlBlock/gen_dcol[1].dc_I} -design DoubleColumn vcd design:ControlBlock syn_generic syn_map write_db -common dbs/merged
However,
- this seems to again synthesize the submodule. (Why? It's marked "preserve")
- Constraints to FFs within the submodule are lost. I only get "No paths found" when I query timing to a FF.
- I might want to completely split out the submodule synthesis to be done at another time.
At this stage I'm stuck at the moment. I do have all the bits and pieces (netlists, SDC, etc), but just can't find the way to combine them.
I can read the toplevel, define the ILM and assemble the design. But that does not bring in the full netlist of the subdesign, which is not contained in the ILM.
I tried starting a new session, reading the DB of the toplevel and then calling create_design to create a second design to try and bring DoubleColumn in from the DB. But this fails when reading the LEFs (Lef files are read when design exists. [PHYS-6187]). I could probably modify the DB to skip reading the physical data by patching the files. But that seems wrong to me.
In principle, I do not care whether assembly takes place in Genus or Innovus, so any solution would be appreciated.
Thanks,
Michael
My sources so far:
¹ https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESqVUAW&pageName=ArticleContent
² https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xyaIEAQ&pageName=ArticleContent