Dear Community
Please consider the following screenshot:
The image shows part of the power grid (MET5 horizontal and MET6 vertical) and a RAM block surrounded by a block ring. The RAM's power pins (horizontal stripes above the block) are connected to its ring.
When I execute
setSrouteMode -viaConnectToShape {ring stripe blockring}sroute -connect {corePin} -corePinTarget {ring blockring stripe} -nets {vddd vssd} -allowLayerChange 1 -allowJogging 0
The following result occurs:
The second image shows a close-up of the righ-hand side of the block ring. Since the standard rows are not necessarely aligned with the power pins of the RAM, it can occure the core pins cannot made a direct connection to the power grid. sroute now places a second via stack, i.e. the via stack from the RAM's power pins and the one from the standard row are overlapping, causing a design rule violation.
Strangely, this only occurs at block rings. There are other situations in the design where the place for a direct via stack is already occupied by something else. For example, power pads that are connected to the core ring. In these cases, sroute simply stops in front of them and places no vias, i.e. it leaves the ends open. They can then be later routed using the -allowJogging 1 argument.
Is there a simple way to prevent these design rule violations? Or is there a command that tries to merge overlapping via stacks?
Thank you.