Bit order after flatten_complex_ports

Hi all!

I have the follow SV structure definition:

typedef struct packed {
  logic [1:0] buf_gain;
  logic [1:0] pre_amp_gain;
} global_bit_t;

This structure is used as the type of a port on my toplevel.

Because I need to load the synthesized design into Virtuoso, I'm calling

flatten_complex_ports [get_db modules top]

during synthesis. I expected that pre_amp_gain[1:0] would be mapped to positions [1:0] of the flat array, and buf_gain[1:0] to [3:2]. In this order.

After completing the flow, I'm writing out the mapping of the port names (.name vs .original_name), and this is what I get:
GLOBAL_BIT[3] GLOBAL_BIT.buf_gain[0]
GLOBAL_BIT[2] GLOBAL_BIT.buf_gain[1]
GLOBAL_BIT[1] GLOBAL_BIT.pre_amp_gain[0]
GLOBAL_BIT[0] GLOBAL_BIT.pre_amp_gain[1]

So the order of the members of the struct is as expected, with pre_amp_gain at 0. But each member's order is exactly opposite of what I expected, which is pre_amp_gain[0] mapped to 0.

Is this the intended behavior? Is there any way to get the result I want? I checked the help system, and there seem to be no settings that affect flatten_complex_ports.

Thanks,
Michael

PS: Genus 22.14-s059_1.