Hey there!! . I found a lot of trouble trying to implement a basic Phase frequency detector circuit in cadence virtuoso using 65nm technology. I have implemented it using a basic D flip flp with a reset input. But the output is not how it is supposed to be
net 10 represents the reset input to both DFF's ,net 25 and net 5 represents the clock inputs
ignore the and and the or gates in the circuit, just consider the clk inputs given to the dff
This is the DFlip flop circuit, i used a glitch removal unit using a buffer and an and gate because i was getting some glitches for S and R (the inputs to the last stage of NAND gates)