Hi all,
I'm running a script that was given to me for clock tree synthesis, but no buffers are being inserted in my clock tree. I only have 240 sinks (flip-flops) and one clock input pin in my design. I suspect the problem is due to my power domain specification, but I cannot figure it out. The basic scheme I am trying to recreate:
The design is primarily an input to reg path, in which I have specified each cell one logic depth before a flip flop to be in a different power domain (via CPF). The reason I created this power domain is that I want those cells to be connected to a virtual rail that I can monitor with a separate analog macro. However, both power domains will be running at the same nominal voltage (0.6 V, and the domain with the virtual rail may see a little drop-but that is not the main concern).
When I try to run: ckSynthesis -rguide ${top_level}.cts.rguide -report ${top_level}.ctsrpt -macromodel ${top_level}.ctsmdl -forceReconvergent
No clock tree buffers are added. I have attached the log file and cts file I am using. I know there is enough space in my design for buffers to be added.
Newbie student here, so ANY advice or help is appreciated. (i'm using 130 nm ibm13, 1.2V but my design is low power/using a library characterized at 0.6 V). Thanks for your time!