Dear all,
I'm currently working on a full-chip mixed-signal design with a digital-on-top approach. The full-chip design hierarchy is in form of structural Verilog that interconnects synthesized digital modules and analogue macros. Actually both synthesized modules and macros are placed deeply into the design hierarchy. As a baseline choice we decided to include all power/ground connectivity already in such a structural Verilog in order to allow analogue designers to immediately generate structural schematics and perform mixed transistor-level/functional verifications without the need of final Encounter gate-level netlists.
All modules of the design include therefore VDD/VSS and AVDD/AVSS port declarations from the beginning, e.g.
module moduleName(
input ...
output ...
inout VDD, VSS,
inout AVDD, AVSS etc. ) ;
and VDD/VSS AVDD/AVSS nets (wires) are propagated through the design hierarchy.
Unfortunately, when we move to Encounter place-and-route we are facing issues in mapping global net connections to these Verilog-defined power/ground nets.
As usual, global power/ground nets are declared during the design import stage with
set init_pwr_net {VDD AVDD}
set init_gnd_net {VSS AVSS}
while the mapping between LEF-defined STD cell pins and top-level power/ground pins in declared with the usual syntax
globalNetConnect VDD -type pgpin -pin VDD -inst * -verbose
globalNetConnect VSS -type pgpin -pin VSS -inst * -verbose
etc.
Furthermore, we tried to map Verilog-defined VDD/VSS and AVDD/AVSS nets to top-level power/ground pins with
globalNetConnect VDD -type net -net VDD -verbose
globalNetConnect VSS -type net -net VSS -verbose
etc.
The problem is that the mapping between Verilog-defined P/G nets is totally ignored (with the -verbose option we see that actually no nets are mapped to top-level VDD/VSS and AVDD/AVSS).
During place-and-route flow a large number of ENCDB-2078 warning is issued to the console because Verilog-defined VDD/VSS and AVDD/AVSS modules pins are just seen as signal pins, with the statement
Output pin VDD of instance XYZ is connected to power net VDD. Usually it is
not right to connect an output signal pin to a P/G net, unless the pin
is meant to be the driver of the net. This can create a short circuit
if the output is %s. Check the connectivity in the netlist.
Now the most annoying problem: when the final netlist is saved to perform signoff LVS checks,
saveNetlist -includePowerGround -excludeLeafCells netlist.v
all connections to STD cells are dumped in form of
.VDD(VDD_0), .VSS(VSS_0)
and new ports VDD_0/VSS_0 are automatically created for all modules, except for the top-level module,
module moduleName(
...
inout VDD, VSS,
inout VDD_0, VSS_0 etc.)
instead of keeping global nets and dumping STD cells P/G connections as .VDD(VDD), .VSS(VSS), which is what I want.
Actually looking at the documentation of the EDI System User Guide (soceUG.pdf), ch 18 - Power Planning and Routing it is stated that:
"Global net connections connect terminals and nets to the appropriate power and ground nets so that
power planning, power routing, detail routing, and power analysis functions operate correctly for the
entire design. Some of these terminals and nets are contained in the Verilog netlist, and others are
contained in the LEF file.
From the Verilog netlist, you can connect the following type of nets to power and ground nets:
Power and ground nets
Connect between the power and ground nets to the appropriate power and ground nets. These
power and ground nets are wire keywords in the Verilog netlist.
Tie-hi and tie-lo nets
Connect between the tie-hi and tie-lo nets to the appropriate power and ground nets. These are
keywords in the Verilog netlist, such as 1'b0 , 1'b1 , supply0 , and supply1 .
Local nets
Connect between the local nets to the global nets. These local nets are wire keywords in the
Verilog netlist. "
So it should be possible to include P/G connectivity in RTL from the beginning.
So the question is how to fix this ?
Thanks in advance
Luca