Hi,
I am trying to run placement on a test block that has many instances of an INVX1, which is 2 columns wide. I have 3 different flavors of INVX1 instances in the design: LVT, RVT and HVT.
Each of these Vt implant layers has a width requirement of at least 3 columns. So if SoC Encounter places in a row:
... [INVX1_RVT] [INVX1_LVT] [INVX1_RVT]...
The INVX1_LVT instance will trigger an LVT MinWidth violation.
My tech lef is coded as following:
LAYER LVT
TYPE IMPLANT ;
WIDTH <my_3_column_width_value> ;
END LVT
My std cell macros contain the obstructions for the Vt layers
MACRO INVX1_LVT
...
OBS
LAYER LVT
RECT 0.000 0.000 <my_2_column_width_value> <my_cell_height> ;
My question is: how to get SoC Encounter to place the cells to avoid MinWidth Vt violations? Encounter can correctly identify the MinWidth DRC violations but placeDesign or addFiller -fixDRC does not seem to solve it or take it into consideration.
The solution I'd expect is to have cells of the same Vt grouped together (or with a filler of the same Vt) to have at least the min width of 3 columns.
Thank you in advance.
Regards.