report_timing after clock tree synthesis shows the same clock to be ideal on capture flop while propagated on the launch flop

Hello Everyone,

After my clock tree synthesis is done, I use "report_timing" command to report the timing paths. I see some of the clocks in the design to be ideal on the capture path while being propagated on the launch path. Could there be some setting I am missing which has resulted into this? Below is one of the failing paths:

Path 219: VIOLATED (-2.235 ns) Setup Check with Pin digtop_scan_inst/dsp_top_inst/ucdsp_subsystem_inst/u_ucdsp_mem_wrapper/u_ucdsp_yram/CLK->WZ
               View: func_QC_MAX_CUSTOM_W_150_1.35_setup
              Group: reg2reg
         Startpoint: (R) digtop_scan_inst/dsp_top_inst/ucdsp_subsystem_inst/u_uCDSP/inst_reg_ACl/reg_val0_reg_25_/clk
              Clock: (R) DSP_CLK
           Endpoint: (R) digtop_scan_inst/dsp_top_inst/ucdsp_subsystem_inst/u_ucdsp_mem_wrapper/u_ucdsp_yram/WZ
              Clock: (R) DSP_CLK

                       Capture       Launch
         Clock Edge:+   12.000        4.000
         Drv Adjust:+    0.432        0.432
        Src Latency:+    3.286        3.995
        Net Latency:+    0.300 (I)    2.436 (P)
            Arrival:=   16.018       10.862

              Setup:-    0.734
        Uncertainty:-    0.300
        Cppr Adjust:+    0.709
      Required Time:=   15.692
       Launch Clock:=   10.862
          Data Path:+    7.065
              Slack:=   -2.235
     

Please note the above highlighted line which shows the net latency. The clock DSP_CLK is reported to be (I) ideal for capture while it is reported to be (P) propagated for launch path. Have I missed some attribute setting?