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eco - Soc Encounter
Hi,Is there any way to execute timing eco file written from Prime Time (Synopsys)?Thanks.
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rda_Input(ui_cdb_file,min)
HI,What are the files that ui_cdb_file,min/max should point to? (for mmmc flow) Thanks.
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Structured datapath (SDP) difficulties
I am trying to use SDP with EDI 13.11 and am running into a problem. Hoping someone can offer some advice; my apologies for the length of this post.* GOALHere's what I want to accomplish:(1) Write an...
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Encounter power rail short
Hello,I am trying to place a big macro in encounter. The macro has its first and last power rail of type vdd!.By default it is placed starting from the gnd! special route rail. So I have a short as...
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Estimating Area & Power of RAM
Hi,I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero...
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problem with sense amplifier detection in ELC
hi all, I am trying to generate .lib for the standard configuration of sense amplifier using encounter library characterizer. but following error appears after db_prepare -f...
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Encounter ENCDB-1256
Encounter generates an error.description man:NAME ENCDB-1256SYNOPSIS Power pin %s of instance %s is connected to non-p/g net %s. Mark the net as power net and create associated...
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Is there a way to specify antenna info for top-level terminals?
Hi, I'm using Encounter to build a digital block. I have placed the top-level terminals using "editPin" commands and that works fine. After building the block and integrating it with the rest of the...
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Can I use just my top metal to create the entire power rings and strap
Hi,Can I create the neite power structure, I mean both horizontal and vertical lines of core rings, vertical strips and horizontal power stripes using a single metal ( top metal). Is this a right...
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Make macro block pin visible in higher hierarchy
Hello all,I have the following situation in SOC Encounter:I have made a design X, which uses some standard cells, and some macro blocks. One type of macro block should have an input or output port....
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3rd party supplier for a standard cell library -> UMC 55nm 3v3
Hello,I'm trying to locate a 3rd party supplier for a standard cell library -> UMC55SP process 3v3 which will be used in the EDI flow. Does anyone know a vendor?
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About timing and slack
Hi, I am using EDI 10.12.002 to implement a processor design. I have my own library of logic cells which I mix with certain sequential cells, buffers and inverters of a vendor library. The geometric...
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The 'UNITS' attribute should be set in the first lef file (technology lef)
Hi everyone, I'm trying to use Cadence Encounter to place and route my design in 130 nm UMC technology. I've already characterized my self-defined standard cell library using ELC. I'm sourcing the .lef...
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verifyGeometry violations, Encounter 11
I'm having a strange issue with verifyGeometry in Encounter 11. After routing my design, my tcl script runs 'verifyGeometry' before saving the design (.enc) . 'verifyGeometry' reports that there are...
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IC5141 CDL in skipping passive devices
Hello everyone, I'm trying to import a CDL netlist that contains IO pads and logic into IC5141. The issue I am having is that it skips all of the passive devices within the cell. This particular cell...
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ELC D-flip flop characterization problem
I am trying to characterize the DFSR (Set reset flip flop) using the Encounter User's Guide (Pages 192-193) version 12.0I have used the two bool file lines for cell recognition: ([N7], [N1], [N4],...
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verifyconnectivity
After doing the verify connectivity, I am getting the error "dangling wires" . Please guide me how to solve the problem
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Is there a way to use CTS with differential (diffpair) clocks?
Hi, I am researching an implementation idea to use Clock Tree Synthesis (CTS) to route a clock tree that consists of a differential clock. The desired results would be a clock tree that is routed as a...
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Creating .lib file for a flipflop
Hi everyone, I'm using ELC to characterize my design library in UMC 130 nm technology. All of my cells except the flipflops have been characterized and I'm getting errors that some of the Hspice...
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route follow pins inside a block ring.
I have a softblock in my design. I want 1) create a block ring for the block "A" and the core ring for other modules skipping the blobk "A". I tried to do this by creating a fence, but encounter don't...
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