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Tempus ECO initial setup summary not matching timing report results

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations....

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UPF 3.1 / Genus - Cannot find any instance for scope

Hi, I'm using genus (Version 21.14-s082_1) to synthesis a VHDL-design with multiple power-domains. After reading the power intent file and calling 'apply_power_intent',  I get the following...

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Off grid violations on M2 layer

Hi all,I have off grid violations on M2 layer. I have tried ecoRoute -fix_drc and deleting violations and rerouting. But the tool is still placing these routes off grid. The on grid option in nanoroute...

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Tid problem

Hi all, while saving design, there is an error saying a net has tid problem. However the design is saved. Does anybody know how to resolve the Tid problem?

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Innovus post CTS Timing Analysis issue

While performing the timing analysis after post-CTS. We are getting warnings on all input ports defined in our design. **WARN: (IMPESI-3095):  Net: 'CLK' has no receivers. SI analysis is not...

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cut_spacing violation

I am getting the cut_spacing violation in the power plan, my design has two power rails, and the via is not formed for two rails, only one rail getting via, I used edit power via and modified the...

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Generate LEF/GDS LayerMap File

I have a standard cell library containing LEF, GDS, and spice models but no OA views. I'm unable to import these files into Virtuoso without a LayerMap file. How can I obtain or generate this required...

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Clock doubler SDC modelling

Hi all,I'm trying to model the clock of a clock doubler. The doubler consists of a delay cell and an XOR gate, which generates a pulse on both the rising and falling edge of the input clock. I've...

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digital implementation on android and ios

With digital implementation rapidly advancing, how do you think iOS and Android platforms will continue to evolve in industries like healthcare or education? The integration of mobile technology is...

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How to quit “[SUSPEND]” in innovus

for debug I use suspend in my tcl script to debug,here is the codeafter that the innovus command screen become how to quit the SUSPEND status? thanks

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Tool to create *.lib and *.db files for designs made in Innovus

Hi all, I have made a custom cell in Innovus that I will be instantiating into a bigger block, which I will also be using Innovus to do the Place & Route. I understand that I can generate a *.lef...

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Find layer map file name and path for a library

I'm trying to write a generic piece of code that will return the layermap file location, with file name, for a variety of projects (which could potential have different layermap file naming...

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How to import different input combination to the same circuit to get max,...

Hi everyone. I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence...

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IR Drop Criteria

IR criteria:Static IR (STD) ~2%Static IR (MEM) ~1%Dynamic IR (STD) ~10%Dynamic IR (MEM) ~5%Anyone knows the reason behind this criteria? >.<

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How to define the pin locations for 2-dimensional input?

I have a 2-dimensional input in my design - input [2:0] data_in [15:0]. After synthesis with genus, I got a netlist where the inputs are like \data[15], \data[14],...,\data[0]. And furthermore it has...

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Always on buffering

Hello All,How do we control the Always on buffering for a power domain called B in Power domain A.here B-power domain nets going through A , hence tool is inserting Always on buffers.How do we avoid...

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Assistance with Followpin Connection to Power Ring

Dear All,As shown in the image below, some followpins (in blue) fail to connect to the power ring. This appears to be because the horizontal tracks connecting the power pad on the right to the power...

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Innovus: Assistance with Followpin Connection to Power Ring

Dear All,As shown in this image, some followpins (in blue) fail to connect to the power ring. This appears to be because the horizontal tracks connecting the power pad on the right to the power ring...

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LEF file error in floorplan

I encountered some problems when running the digital flow example by foundry, which actually complaining about the lef file in the library. These error are gotten with all the inputs from Stylus...

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Captablefile

What  does Ctot means and how it been calculatedwidth(um)  space(um) Ctot(Ff/um)  Cc(Ff/um)    Carea(Ff/um) Cfrg(Ff/um)0.070       0.052       0.1986       0.0723       0.0311       0.01150.070...

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