i want to test iscas benchmark circuits i have verilog file for that how to convert to spice netlist![]()
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converting verilog to SPICE netlist
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verifyGeometry violations, Encounter 11
I'm having a strange issue with verifyGeometry in Encounter 11. After routing my design, my tcl script runs 'verifyGeometry' before saving the design (.enc) . 'verifyGeometry' reports that there are multiple violations of various types. However, if I reopen Encounter and load the design (.enc) and rerun 'verifyGeometry', there are no violations detected.
After I save the design (through OA) into one of my Virtuoso libraries, I run Calibre DRC and LVS. The only DRC errors reported are density related. LVS passes.
Does anyone have any idea why verifyGeometry is reporting these violations before closing restarting Encounter?
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verifyconnectivity
After doing the verify connectivity, I am getting the error "dangling wires" . Please guide me how to solve the problem
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route follow pins inside a block ring.
I have a softblock in my design. I want
1) create a block ring for the block "A" and the core ring for other modules skipping the blobk "A". I tried to do this by creating a fence, but encounter don't exclude fence, it dumps an error to chech placement status of fence :(
2) I want to create a separate stripe for block ring
3) I want the block rings to have separate follow pins . Please tell me how I can do this without CPF.
thanks
gops
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Short between IO filler blockage and IO pad pin
Hi,
In our design we have IO fillers with blockage for the IO ring power & ground stripes, and IO pads with pins for the same busses. When placing fillers between the IO cells, we see short violations between the pad pins and the filler blockages (see attached image). How can we fix or ignore these violations?
The LEF for the IO filler and pad looks like:
MACRO IOFILLER
...
OBS
LAYER M3 ;
RECT 0.00 78.50 5.60 104.06 ;
...
MACRO IOPAD
CLASS PAD ;
SITE IO ;
PIN VDD!
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M3 ;
RECT 0.00 78.82 75.04 83.58 ;
..
Link to GUI image: http://i42.tinypic.com/33di5jc.gif
Thanks in advance,
/Max
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Fixing Transition violations
1. I was trying to fix transition violation using -drv, for a design with fences and guides. But I was in wain. Once I removed them
and recreated the encounter database with DEF, and V. The encounter was able to fix them.
2. I removed the fences and groups using encounter (from floorplan menu) and saved the database. But some thing was blocking it to fix the transisition. The '.tran" file read something to do with "setDoAssign" ?
But go through the flow, I had to again, exit and recreate the database.
Did any one experience such a thing. What I am doing wrong here.
Thanks a lot in advance for your help !!
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Encounter final layout export to Cadence Virtuoso
Hello,
I am now starting to read and going through the process of digital flow.
What is the best way to export the final routed and placed design in encounter to Cadence Virtuoso environment for the subsequent DRC and LVS?
As far as I saw already from several manuals, one way is to save the GDS, then go through the process of importing GDS inside Virtuoso in a new library, a process with which I am familiar with. Then of course one can perform DRC there with Assura. And then if I am correct, that library can be used in any of a custom designed analog block in another library within Virtuoso environment.
But question is, what if the digital design was fully done using the HDL (vhdl or verilog), how does one perform LVS then once the GDS was imported in the Cadence Virtuoso environment?
When I design analog circuits, LVS compares my custom layout against the CDL-type netlist which is generated from the schematics I manually build.
But if I imported the GDS layout of automatically placed and routed digital design by encounter, how do I set up the process for LVS to compare it with HDL description? Or in what other proper way this has to be done?
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usage of standard cell libraries in Encounter
Hello,
I have already followed successfully some manual which basically talks about how to import the Verilog design which references the standard cell primitives contained in the LEF file. So I import the LEF file, and the .v file, and get the whole thing placed and routed. But that manual is about some generic NCSU-type format.
I now want to try similar thing, but specific to my design kit. The design kit is just a PDK from IBM for 7rf process.
I opened the LEF file provided by the kit, and noticed that there are no standard cell primitives description, as it was a case with LEF file from NCSU with which manual I followed was provided. All I find in the Design Kit's LEF file is description of some rules and layers.
So I assume that there has to be a way of entering the standard cell primitives in that LEF file?
If yes, then what is the smart and proper way of doing it?
Design kit also provides HDL files for the timing/behavior description of each standard cell as well as one big GDS file.
What would be the typical flow to make it all functional? in other words, to somehow let the encounter know about my standard cell files? (again because Design Kit's LEF file has only layer/rule iniformation)
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Ports mismatch
Hi ,
I am running LVS, I have assigned ports in the desing but still in LVS report layout has 0 ports. I am working on Encounter10.13
dv_obj_count -transformed_nets {132639 59910} -transformed_inst {180591 116168} -transformed_port {0 423}
dv_discrep 1 {Incorrect Nets}
I am using the below command to save the netlist.
saveNetlist design.v -excludeLeafCell -includePowerGround -excludeLogicalCell {FILL16BWP FILL8BWP FILL4BWP FILL2BWP FILL1BWP} -includePhysicalCell {GDCAP4BWP GDCAP2BWP GDCAP3BWP GDCAP4BWPLVT GDCAP10BWP GDCAP3BWPLVT GFILL3BWP GFILL2BWP GFILL4BWP GFILL3BWPLVT GFILL2BWPLVT GFILL4BWPLVT GFILL10BWP} -replaceTieConnection
Kindly help me on this.
Thank you.
Regards..
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ETS Flow CCS versus NLDM models
Hello All,
We have been using NLDM models for a long time now.Our ETS Flow tuned with NLDM models, closely compares with third party sign-off tool and the timing difference most of the times is within 2%.
However, the same flow, does not compare well with CCS models. We are seeing 3-5% timing difference between ETS and third party tool.
Can someone suggest on how CCS/ECSM correlate with silicon results. Should we definitely consider moving to CCS, if yes why?
Let me know if you need more information.
Thanks and Regards,
Mali
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PnR tips, macros placement
Hi !
I'm new to floorplanning, and PnR in industry level. Can someone please help me with some tips from your experience, and where to find useful examples for macros placement, some kind of things you do to prevent congestion, and make your design more robust. Thanks a lot !
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Classification of nets in DEF
Can anyone help me understand why there are classifications of NETS, PINS, and SPECIALNETS in DEF?
I am looking at the Cadence 13.14 EDI LEF/DEF Language Reference manual - version 5.8, March 2013.
It shows the following for NETS (and something very similar for PINS and SPECIALNETS) :
---------------------------------------------------------------------
NETS numNets ;
......
[+ USE {ANALOG | CLOCK | GROUND | POWER | RESET | SCAN | SIGNAL
| TIEOFF}]
---------------------------------------------------------------------
And it has the following description:
---------------------------------------------------------------------
USE {ANALOG | CLOCK | GROUND | POWER | RESET | SCAN | SIGNAL | TIEOFF}
Specifies how the net is used.
Value: Specify one of the following:
ANALOG Used as an analog signal net.
CLOCK Used as a clock net.
GROUND Used as a ground net.
POWER Used as a power net.
RESET Used as a reset net.
SCAN Used as a scan net.
SIGNAL Used as a digital signal net.
TIEOFF Used as a tie-high or tie-low net.
---------------------------------------------------------------------
Having these classifications seems like a good idea (and they seem to be mentioned at least as far back as SOC8.1USR3's LEF/DEF Language Reference version 5.7 from June 2009). However, I don't know of any way to set, modify, or query them from within EDI.
Is this possible? Thanks!
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Is post CTS optdesign command optimizes clock path.
optdesign -postcts .
Is the above command optimizes clok path.I am not using useful skew in setoptmode.
According to my understanding it only optimizes datapath not clockpath.
If we set setoptmode usefulskew true, then only optdesign optimize clock path.
Can anyone clarify this or correct me.
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How to optimize level shifter and isolation instances marked dont touch in Encounter
Hi All,
I am implementing a Low-power design with Power switches and Isolation cells. I have a CPF file that I commit and I can see that isolation cells and level shifters are inserted into the design correctly as I intended.
However, whenever I run optDesign, whether it be preCTS, postCTS or postRoute, Encounter seem to mark level shifters and isolation instances as don't touch instances and does not optimize them. As a result, the drive strength of the isolation instances are too small. I know that Encounter doesn't optimize clock nets but there is a ckECO option to take care of clock optimization. Is there a way to make Encounter optimize the level shifter and isolation instances and/or remove the dont touch marking on these instances?
Below are the messages I get in the log file when I run optDesign :
*info: Marking 12 level shifter instances dont touch
*info: Marking 64 isolation instances dont touch
I've tried to use set_dont_touch and set_interactive_constraint_mode options to override this but haven't succeeded so far. Has anybody gotten the same problem and does anybody know how to solve this?
Thanks
Saekyu
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Virtuoso 6.1.5 to encounter
Hi All,
I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.
=====================================================
--> <folderPath>/BackEnd/
* LEF P & R model (in <folderPath>/BackEnd/lef)
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.3.lef
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.lef
- foa0i_r33_t33_generic_io.3.lef
- foa0i_r33_t33_generic_io.lef
- header3_V55.lef
* physical compiler database (in <folderPath>/BackEnd/phycompiler)
- foa0i_r33_t33_generic_io.3.pdb
- foa0i_r33_t33_generic_io.3.plib
--> <folderPath>/TECH/
* Cadence DFII environment files (in <folderPath>/TECH/dfii)
- FOA0I_R33_44.tf
- cellout.tab
- display.drf
- layer.DEFINE
- pg_sout3.tab
- pg_sout4.tab
- streamOut.map
- streamin.tab
- txtfont.tab
====================================================
Which is better out of the two options
1. Do IO placement in virtuoso itself
2. Take it to encounter - (How to do it ?)
Thanks,Shameel
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Virtuoso 6.1.5 to encounter
Hi All,
I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.
=====================================================
--> <folderPath>/BackEnd/
* LEF P & R model (in <folderPath>/BackEnd/lef)
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.3.lef
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.lef
- foa0i_r33_t33_generic_io.3.lef
- foa0i_r33_t33_generic_io.lef
- header3_V55.lef
* physical compiler database (in <folderPath>/BackEnd/phycompiler)
- foa0i_r33_t33_generic_io.3.pdb
- foa0i_r33_t33_generic_io.3.plib
--> <folderPath>/TECH/
* Cadence DFII environment files (in <folderPath>/TECH/dfii)
- FOA0I_R33_44.tf
- cellout.tab
- display.drf
- layer.DEFINE
- pg_sout3.tab
- pg_sout4.tab
- streamOut.map
- streamin.tab
- txtfont.tab
====================================================
Which is better out of the two options
1. Do IO placement in virtuoso itself
2. Take it to encounter - (How to do it ?)
Thanks,Shameel
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Clock Tree Synthesis - Not able to add clock buffers
Hi all,
I'm running a script that was given to me for clock tree synthesis, but no buffers are being inserted in my clock tree. I only have 240 sinks (flip-flops) and one clock input pin in my design. I suspect the problem is due to my power domain specification, but I cannot figure it out. The basic scheme I am trying to recreate:
The design is primarily an input to reg path, in which I have specified each cell one logic depth before a flip flop to be in a different power domain (via CPF). The reason I created this power domain is that I want those cells to be connected to a virtual rail that I can monitor with a separate analog macro. However, both power domains will be running at the same nominal voltage (0.6 V, and the domain with the virtual rail may see a little drop-but that is not the main concern).
When I try to run: ckSynthesis -rguide ${top_level}.cts.rguide -report ${top_level}.ctsrpt -macromodel ${top_level}.ctsmdl -forceReconvergent
No clock tree buffers are added. I have attached the log file and cts file I am using. I know there is enough space in my design for buffers to be added.
Newbie student here, so ANY advice or help is appreciated. (i'm using 130 nm ibm13, 1.2V but my design is low power/using a library characterized at 0.6 V). Thanks for your time!
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UltraSim simulation issue for Power-up Rush Current Analysis with Power Gate(Switch)
Hi All,
I'm trying to run a rush current Analysis for a power-gated design I am implementing. I've been going through the Encounter and EPS manual to set the analysis up properly and I don't think I'm doing anything wrong...But whenever I run the power-up (rush current) analysis, EPS (or Encounter) produces an ultraSim RC parasitic spiceDeck (Switched_Net.rc) for the design that has a ton of duplicate instantiations and it kills the ultraSim simulation. This is the Error message I'm getting in the Switched_Net.ulog file :
ERROR (SFE-401): Duplicate instantiation of 'RC_instance...' in 'Design'
I get this error for almost all nets in the design so the spiceDeck creation is messed up but I'm not sure why. The spiceDeck generation process is automated within the power-up analysis flow so I'm not sure why it is doing what it's doing.
Has anybody had a simular experience with the Power-Up analysis in Encounter and know how I can solve this issue?
Thanks
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TI, Ultralibrarian, Orcad 10.5 and Pspice
Hi everybody,
I want to simulate the IC : SN74CBT3125C dowloaded from : http://www.ti.com/product/sn74cbt3125
I downloaded the bxl file, used the ultra librarian to get the edif file for Orcad, and now I want to simulate it on Pspice, but it tells me that it does not recognise this component!!
Please help me, I spend a lot of time on it!!
Think you!!![]()
I want to simulate the IC : SN74CBT3125C dowloaded from : http://www.ti.com/product/sn74cbt3125
I downloaded the bxl file, used the ultra librarian to get the edif file for Orcad, and now I want to simulate it on Pspice, but it tells me that it does not recognise this component!!
Please help me, I spend a lot of time on it!!
Think you!!
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IO boundary for rectilinear floorplan
So I have a DEF file which when loaded gives a rectilinear core shape. But when I specify the core to IO boundary spacing, the core reshapes into the default square shape. How can this be prevented from happening?
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