My log file shows: "environment variable TMPDIR is '/tmp/" 

When in the flow should I:

' setenv TMPDIR /user/me/tmp '

...to prevent EPS from using the /tmp/ directory on our machines.

HI, All

 Now, I want to characterize a level shifter cell with two supplys by ELC of ETS11.0, but I have no idea to setup the voltage for the two supplys respectively,I only know how to set the default operating voltage. Could anyone  tell me about it ?  Thank you for that.

  Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4

/* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";}

Hello

I am trying to compile a top level design. This top level design contains sub-blocks.

All the sub-blocks apart from one are compiled into the default directory, WORK.

One sub-block is compiled in a different directory, WORK_ECU

The configuration is defined as follows:

library work;

library work_ecu;

-- ---------------------------------------------------------------------------------------------------------------------------------

-- entity name: uccp_block1_mcp_gram_cfg

-- purpose: Universal Communications Core Platform (UCCP) Synthesis/Layout Block 1 configuration

-- ---------------------------------------------------------------------------------------------------------------------------------

configuration uccp_block1_mcp_gram_cfg of uccp_block1_mcp_gram is

   for rtl

      for all : img2_resetn_ip_sync

         use configuration work.img2_resetn_ip_sync_cfg;

      end for;

      for gen_mcp_rst

         for all : img2_resetn_ip_sync

            use configuration work.img2_resetn_ip_sync_cfg;

         end for;

      end for;

      for all : uccp_sysbus_addr_dec_block1

         use entity work.uccp_sysbus_addr_dec_block1(rtl);

      end for;

      for all : uccp_pbus_addr_dec_block1

         use entity work.uccp_pbus_addr_dec_block1(rtl);

      end for;

      for gen_mcp

         for gen_mcp_i

            for all : mcp_top

               use configuration work.mcp_top_cfg;

           end for;

         end for;

      end for;

      for gen_ecu

         for all : uccp_mips_ecu_wrap

           use configuration work_ecu.uccp_mips_ecu_wrap_cfg;

         end for;

      end for;

I have updated the hdl.var as follows:

INCLUDE $CDS_INST_DIR/tools/inca/files/defaults/hdl.var

DEFINE WORK pvrlib

DEFINE WORK_ECU mips_ecu_lib

DEFINE NCSIMRC ncsimrc

I have updated cds.lib as follows:

SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.lib

DEFINE pvrlib   ./pvrlib

DEFINE mips_mcu_lib ./mips_mcu_lib

DEFINE mips_ecu_lib ./mips_ecu_lib

When I try to compile the code, I get the following error:

cvhdl -v93 -error 5 -nocopy -work pvrlib  ../../src/main/uccp_block1_mcp_gram.vhd

ncvhdl -v93 -error 5 -nocopy -work pvrlib  ../../src/config_cfg0043/uccp_block1_mcp_gram_cfg.vhd

library work_ecu;

               |

ncvhdl_p: *E,LIBNOM (../../src/config_cfg0043/uccp_block1_mcp_gram_cfg.vhd,21|15): logical library name must be mapped to design library [11.2].

            use configuration work_ecu.uccp_mips_ecu_wrap_cfg;

                                     |

ncvhdl_p: *E,IDENTU (../../src/config_cfg0043/uccp_block1_mcp_gram_cfg.vhd,54|37): identifier (WORK_ECU) is not declared [10.3].

make: *** [.vmkr_Linux/uccp_block1_mcp_gram_cfg_uccp_block1_mcp_gram.ana] Error 1

[1] 4261

Exiting with status code 2

Any thoughts or pointers appreciated.

Thanks

JO

Hi, I want to know what  "Minarea violation" is, and how can I solve it?? I have 3 Minarea violations in Geometry verifying by SOCencounter... 

thanks alot 

I am new to soc encounter, Can anyone guide me how to do the design partition flow. Due to lincese problem It does not read the Power domain (Low power) commands, MSMV and cpf file.

The design TOP has two modules u00 and u01. These two modules has separate external power suply. How to separate these two mdoules in the core? 

How to move the module inside the core area after loading the design?

I started with the commands, 

createFence u00 7 7 16 45
definePartition -hinst u00 -coreSpacing 1.0 1.0 1.0 1.0 -railWidth 0.0 -minPitchLeft 0 -minPitchRight 0 -minPitchTop 0 -minPitchBottom 0 -reservedLayer { 1 2 3 4 5 6 7 8} -pinLayerTop { 2 4 6 8} -pinLayerLeft { 3 5 7} -pinLayerBottom { 2 4 6 8} -pinLayerRight { 3 5 7} -placementHalo 0.0 0.0 0.0 0.0 -routingHalo 0.0 -routingHaloTopLayer 8 -routingHaloBottomLayer 1
createPtnCut -ptn u00 7 7 12 45

Thank you, 

Hello everyone, 

 I'm trying to import a CDL netlist that contains IO pads and logic into IC5141. The issue I am having is that it skips all of the passive devices within the cell. This particular cell has 3 active MOS devices, 3 diodes, and a resistor. CDL in appears to run correctly, but upon checking the schematic, only the 3 transistors are present. Below is the appropriate snippet of the CDL file, my Device Map file, and my ni.log file. I cannot see any reason for the import process to be skipping the passive devices. Please let me know if any additional information or details are needed. 

Thank you!

 P.S. I couldn't find a way to enclose the text in a code box, so please excuse the wall of text.

-----------------CDL FILE----------------------

.SUBCKT IDDBREAK VDD VSS VSSIO

*.PININFO VDD:B VSS:B VSSIO:B

RR0 VSS net40 169.876K $SUB=VDD $[RNPPO_SP] $W=500n $L=204.91u

MNM4 VDD net40 net49 VSS NA W=40e-6 L=120n M=4

MNM0 VSS VSS VDD net49 NA W=40e-6 L=120n M=12

DD2 VSSIO VSS DP 2e-11 4.2e-05 M=5

DD0 VSS VSSIO DP 2e-11 4.2e-05 M=5

DD1 VSS VDD DP 2e-11 4.2e-05 M=5

MPM0 VDD net40 VDD VDD PR W=3e-6 L=4u M=12

.ENDS

-------------------DEVICE MAP FILE-------------------------------

devMap := nfet N_11_SPHVT

propMatch := subtype NH

devMap := pfet P_11_SPHVT

propMatch := subtype PH

devMap := nfet N_25_SP

propMatch := subtype NR

devMap := pfet P_25_SP

propMatch := subtype PR

devMap := nfet N_11_SPRVT

propMatch := subtype NA

devMap := pfet P_11_SPRVT

propMatch := subtype PA

devMap := diode DIOP_SP

propMatch := subtype DP

devMap := diode DION_SP

propMatch := subtype DN

-----------------ni.log--------------------------

==========================

Subckt: IDDBREAK

==========================

Created the CV IDDBREAK->netlist_tmp.

#####################################

MOS Instance: MPM0

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to P_25_SP->symbol.

Now, searching for the cellview P_25_SP->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: P_25_SP->symbol.

instName->'MPM0' is created.

propName->'subtype'; propVal->'PR' is created.

propName->'w'; propVal->'3E-06' is created.

propName->'l'; propVal->'4E-06' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MPM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM0

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM0' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MNM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'net49' of instance 'MNM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM4

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM4' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'4' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MNM4' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MNM4' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'net49' of instance 'MNM4' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VSS' of instance 'MNM4' has been connected to the terminal 'B'.

INFO (CDLIN-54): CDL In successfully created the schematic view IO_lib_SP_2_5V_Inline_Reg_VT.IDDBREAK::netlist. Read the log file 

'conn2sch_IDDBREAK.log' for more information.

I am trying to import a synthesized verilog netlist to virtuoso (IC615). The problem I have is, the standard cells are missing. I do not know what library file I should add to the library manager, as there is no libraray definition in the design kits/examples/cds.lib.

 The design kits I am using is IBM CMOS7RF. It seems that the synthesize library for Synopsys cannot be used in Cadence Virtuoso.

 Thank you for your help. 

Dear,

 I am trying to run (IRUN) script to generate a vcd file inside many folders so my script is like that :

----------------------------------------------------- 

 #!/bin/tcsh

#created @aa835

# script to generate vcd file in each folder 

foreach i(*)

echo $i

irun -v93 *.v *.vhd *.vhd -TOP darcTB - exit

end

ELC seems to always read in files as spice format even though I have "simulator lang = spectre" without the quotes at the top of every .scs file.  In addition I have:

set_var EC_SIM_NAME "spectre"
set_var EC_SIM_TYPE "spectre"

in my script every time before I do any database operation.

These are the types of warnings and errors I am getting (list is really 50x longer mostly referenceing ASSERT.  this is just the end of it):

 [WARNING(db_prepare)] spice syntax warning: ASSERT : no definition of the subckt
 => XVBD_CHECK ASSERT
[WARNING(db_prepare)] spice syntax warning: ASSERT : no definition of the subckt
 => XVBS_CHKFWD ASSERT
[WARNING(db_prepare)] spice syntax warning: ASSERT : no definition of the subckt
 => XVBD_CHKFWD ASSERT
[WARNING(db_prepare)] spice syntax warning: PINMOD : no definition of the subckt
 => XD A C SX PINMOD
[ERROR(db_prepare)] spice syntax error: DIODENWX : illegal port definition of macro
 => XAVD364_1 SUB VDD GND DIODENWX

Notice that is says spice every time instead of spectre.  Maybe this is just a program issue where it always says that spice is used even if it's not, but I have no idea.

So is spice really be used?  And if so then how do I make it use spectre?

Halo, 

I am using ELC to characterise a new standard cell library. I am using a SPECTRE .scs model file, but it seems that ELC is not recognising this file format correctly, as it complains about library and section declarations which are present in the model file. I assume that my command and/or elccfg file is not set up correctly for using spectre. 

This is the contents of my command file:

db_open cell_digital
db_prepare -f
db_spice -s spectre -keep_log -keep_wave
db_output -lib cell_digital.lib -process typical -state
db_close
exit

And this is the contents of my elccfg file:

# Specify the environment variable settings.
EC_SIM_USE_LSF=1;
EC_SIM_LSF_CMD=" ";
EC_SIM_LSF_PARALLEL=10;
EC_SIM_TYPE="spectre";
EC_SIM_NAME="spectre";
EC_SPICE_SIMPLIFY=1;
EC_CHAR="ECSM-TIMING ECSM-POWER";


SUBCKT="cell_digital_SPICE_netlist.scs";
MODEL="model_file.scs";
SETUP="setup.ss";
PROCESS="typical";

Can somebody guide me into the right direction?

Thank you,

Hi,

 I am trying out ELC and found one issue, db_spice couldn't pass, output looks like below:

elc>  db_spice -s spectre -p typical -keep_log -keep_wave

   DESIGN        PROCESS       #ID         STATUS     IPDB

-------------+-------------+----------+--------------+-----------

INVX1          typical       D0000         SIMULATE     foo

INVX1          typical       D0001         SIMULATE     foo

============|=============|=============|==========|==============

INVX1          typical       2          2            foo

NAND2X1        typical       D0000         SIMULATE     foo

NAND2X1        typical       D0001          PASSED      foo

NAND2X1        typical       D0002         SIMULATE     foo

NAND2X1        typical       D0003          PASSED      foo

NAND2X1        typical       D0004         SIMULATE     foo

NAND2X1        typical       D0005          PASSED      foo

NAND2X1        typical       D0006         SIMULATE     foo

NAND2X1        typical       D0007          PASSED      foo

while encounterlc.log/foo.log/*.log says

 Simulation deck created in /home/eda1/ELC/encounterlc.work/foo.work/INVX1_typical_D0000

Using command spectre

Simulation failed with the status 25600

Releasing lock 

the corresponding .lis file says:

Aggregate audit (4:34:48 PM, Thur Jul 24, 2014):

Time used: CPU = 1.17 s, elapsed = 1.17 s, util. = 100%.

Time spent in licensing: elapsed = 798 ms, percentage of total = 68.3%.

Peak memory used = 46.8 Mbytes.

spectre completes with 0 errors, 0 warnings, and 0 notices. 

Seems simulation passed without an issue.

I am really puzzled, could someday let me know what I should do in order to debug this?

I am using ETS10.1 + MMSIM7.2,  haven't found version compatible information in ELC document either.

 Thanks! 

 hello.

I use ELC to character INV and NAND2,when I type db_spice ,it shows 

   DESIGN        PROCESS       #ID         STATUS     IPDB
-------------+-------------+----------+--------------+-----------
INVX1          typical       D0000         SIMULATE    foo        
INVX1          typical       D0001         SIMULATE    foo        
============|=============|=============|==========|==============
INVX1          typical       2          2            foo        
NAND2X1        typical       D0000         SIMULATE    foo        
NAND2X1        typical       D0001         SIMULATE    foo        
NAND2X1        typical       D0002         SIMULATE    foo        
NAND2X1        typical       D0003         SIMULATE    foo        
NAND2X1        typical       D0004         SIMULATE    foo        
NAND2X1        typical       D0005         SIMULATE    foo        
NAND2X1        typical       D0006         SIMULATE    foo        
NAND2X1        typical       D0007         SIMULATE    foo        
============|=============|=============|==========|==============
NAND2X1        typical       8          8            foo        
--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
 2014-07-23 16:21:58 (2014-07-23 08:21:58 GMT) : Vectors Launched 10/10
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary               
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1          typical       D0000     SIMULATE     FAIL        foo        
INVX1          typical       D0001     SIMULATE     FAIL        foo        
NAND2X1        typical       D0000     SIMULATE     FAIL        foo        
NAND2X1        typical       D0001     VERIFICATE   PASS        foo        
NAND2X1        typical       D0002     SIMULATE     FAIL        foo        
NAND2X1        typical       D0003     VERIFICATE   PASS        foo        
NAND2X1        typical       D0004     SIMULATE     FAIL        foo        
NAND2X1        typical       D0005     VERIFICATE   PASS        foo        
NAND2X1        typical       D0006     SIMULATE     FAIL        foo        
NAND2X1        typical       D0007     VERIFICATE   PASS        foo        
-------------+-------------+----------+------------+----------

[INFO(db_spice)] Check the encounterlc.log/<ipdb_name>/<DESIGN>_<PROCESS>_<ID>.log file to determine the cause of the failure. The SPICE simulation log file can be found in the /home/IC_design/VLSI/ELC/encounterlc.work/<DESIGN>_<PROCESS>_<ID>/ directory.

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
 - Total Simulation : 10
 - Total Passed     : 4(40.00%)
 - Total Failed     : 6(60.00%)
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

and My dut,scs is

simulator lang=spectre

subckt NAND2X1 in1 in2 out vdd gnd
    \+3 (vdd in2 out vdd) tsmc25P w=4.5e-06 l=3e-07 as=2.025e-12 \
        ad=3.375e-12 ps=9e-07 pd=6e-06 m=1 region=sat
    \+2 (out in1 vdd vdd) tsmc25P w=4.5e-06 l=3e-07 as=3.375e-12 \
        ad=2.025e-12 ps=6e-06 pd=9e-07 m=1 region=sat
    \+1 (out in2 _6 gnd) tsmc25N w=2.7e-06 l=3e-07 as=1.215e-12 ad=2.025e-12 \
        ps=9e-07 pd=4.2e-06 m=1 region=sat
    \+0 (_6 in1 gnd gnd) tsmc25N w=2.7e-06 l=3e-07 as=2.025e-12 ad=1.215e-12 \
        ps=4.2e-06 pd=9e-07 m=1 region=sat
ends NAND2X1

subckt INVX1 in out vdd gnd
    \+1 (out in vdd vdd) tsmc25P w=4.5e-06 l=3e-07 as=3.375e-12 \
        ad=3.375e-12 ps=6e-06 pd=6e-06 m=1 region=sat
    \+0 (out in gnd gnd) tsmc25N w=2.7e-06 l=3e-07 as=2.025e-12 ad=2.025e-12 \
        ps=4.2e-06 pd=4.2e-06 m=1 region=sat
ends INVX1
~       

my setup.ss is ~

Process typical {
        Voltage = 2.5;
        temp = 25;
        Corner = "TT";
        Vtn = 0.67;
        Vtp = 0.92;
};

Process best {
        voltage = 5.5;
        temp = 0;
        Corner = "FF";
        Vtn = 0.63;
        Vtp = 0.89;
};
Process worst {
        voltage = 4.5;
        temp = 125;
        Corner = "SS";
        Vtn = 0.71;
        Vtp = 0.92;
};
Signal  std_cell {
        unit = REL;
        Vh = 1.0 1.0;
        Vl = 0.0 0.0;
        Vth = 0.8 0.8;
        Vsh = 0.8 0.8 ;
        Vsl = 0.2 0.2;
        tsmax = 2.0n;
};
Signal  std_cell_6710 {
        unit = REL ;
        Vh = 1.0 1.0 ;
        Vl = 0.0 0.0 ;
        Vth = 0.3 0.7 0.3 0.7;
        Vsh = 0.8 0.8 ;
        Vsl = 0.2 0.2 ;
        tsmax = 2.0n;
};
Signal VDD5.0V  {
       unit = ABS ;
       Vh = 5.0 5.0 ;
       Vl = 0.0 0.0 ;
       Vth = 2.5 2.5 ;
       Vsh =  2.0 2.0 ;
       Vsl = 0.5 0.5 ;                         tsmax = 2.0n;
};

Signal VDD2.5 {

       unit = ABS ;
       Vh  = 2.5 2.5 ;
       Vl = 0.0 0.0 ;
       Vth = 1.25 1.25 ;
       Vsh = 2.0 2.0 ;
       Vsl = 0.5 0.5 ;
       tsmax = 2.0n ;
 };
Simulation std_cell {
           transient = 0.1n 80n 10p ;
           dc = 0.1 4.5 0.1 ;
           bisec = 6.0n 6.0n 100p ;
//           resistance = 10K ;
           resistance = 10MEG;
};
Index DEFAULT_INDEX {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
Index X1 {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
Index X4 {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.1p 0.2p 0.4p 1.2p 2.4p;
};
Index IO5*5 {
      Slew = 0.1n 0.3n 0.6n 1.3n 3.0n ;
//      Load = 5p 10p 20p 50p 75p;
       Load = 0.05p 0.10p 0.20p 0.50p 0.75p;
};
Group POWR {
      PIN = *.Vdd *.Vdd2;
};
Group Core_Pins {
      PIn = *.DO *.DI ;
};
Group Pad_Pins {
      PIN = *.YPAD;
};
Group Clk_Slew {
       PIN = *.CLK ;
};

Group X1 {
      CELL = 8X1;
};
Margin m0 {
       setup = 1.0 1.0 ;
       hold = 1.0 1.0 ;
       release = 1.0 1.0 ;
       removal = 1.0 0.0 ;
       recovery = 1.0 1.0 ;
       width = 1.0 1.0 ;
       delay = 1.0 1.0 ;
       power = 1.0 0.0 ;
       cap = 1.0 0.0 ;
};
Norminal n0 {
         delay = 0.5 0.5 ;
         power = 0.5 0.5 ;
         cap = 0.5 0.5 ;
};
set process (typical ,best , worst ) {
         simulation =std_cell ;
         signal = std_cell_6710;
         margin = m0;
         norminal = n0;
};
set index (typical ,best , worst ) {
          Group(X1) = X1;
          Group(X4) = X4;
          Group(Pad_Pins) = IO5*5;
          Group(Core_Pins) = X4;
          Group (Clk_Slew) = Clk_Slew ;
};
set signal (typical ,best ,worst ) {
           Group(POWR) = VDD2.5V ;
};
 

can anyone help me solve this , >_<,   thanks

Liu

Hi,

I am currently creating a LPA flow from 28nm. I was reading the user guide of this tool. It primarily detects hotspots.

What are these hotspots ?  Please explain in detail or point me to any material with information. Thanks !

I am designing a digital block which has stripes on the top metal used to route signals over the block. I created them with the addstripes command. The stripes are connected to a floating output pin of the digital block and specified as a gnd net. This is done via the 

set rda_Input(ui_gndnet"pin name").  

  Now my concern is whether the parasitic effect of the floating top metal is considered in timing analsysis or not. 

To confirm i extract spefs with and without the stripes (same encounter run), but the capacitances are exactly the same. I can see the capacitance to drop to 0 for the net name(without stripes added). I have enabled coupled capacitances too.

Can someone give any ideas on how to confirm that the capacitance is actually used in timing checks.

Thanks and best regards

 Hello,

I am a little confused about an issue. At the design of a 3D ic is it possible to have I/O pads at all the different layers? I have see many algorithms (i.e. for partition, placement) claiming that you can have I/O pads at every layer. In the other hand, i have heard that by manufacruring aspect you can have I/O pads only to one layer. Which scenario is the most reliable? Also, if you can give me a refference it would help too.

thanks.

Hi,

I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that
**ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO.

Here pad inastant name is "clk_in" and pin name is "ANAIO".

Clock tree specification file is

        AutoCTSRootPin clk_in/ANAIO

        NoGating rising               # (for auto CTS on a net)
        Buffer HS65_LS_BFX2 HS65_LS_BFX4 HS65_LS_BFX7 HS65_LS_IVX2 // name of buffer used for CTS
       
       MaxDelay 5ns
       MinDelay 0ns
       MaxSkew 50ps
       End

Hi there,

we are using EPS to generate power reports for a gatelevel netlist produced by EDI. A comparing EDI power reports and EPS power shows big differences in the switching power (see below).

Where do these differences in the switching activity come from, since we are using the same netlist, and the same setup?

EPS report_power with test.vcd for switching acctivity (mW, %)

Total Internal Power:       18.06020172      73.3519%
Total Switching Power:       4.23011635    17.1807%
Total Leakage Power:         2.33098969       9.4674%
Total Power:                24.62130789

EDI report_power with test.vcd for switching acctivity (mW, %)

Total Internal Power:       18.41854781      66.1447%
Total Switching Power:       7.09351231    25.4742%
Total Leakage Power:         2.33379140       8.3811%
Total Power:                27.84585164

report_power script used within EDI and EPS: 

    reset_power_activity
    read_activity_file -reset
    set_analysis_view -setup v_setup -hold v_hold
    set_power_analysis_mode -analysis_view v_setup -method static
    set_dc_sources -power gnd -voltage 0.0
    set_dc_sources -power vdd -voltage 1.0
    read_activity_file $programlist.vcd -format VCD -reset -report_missing_nets true -scope coreva_cpu_system_tb/coreva_cpu_generic_bus_wrapper_1
    report_power -outfile powerReports/$programlist.pwr
 

Here is our setup for EPS (same as in EDI):

read_lib -min $::env(SOC_MIN_TIMELIB)
read_lib -max $::env(SOC_MAX_TIMELIB)
read_lib -lef $::env(SOC_LEF_FILE)
read_verilog coreva_cpu_generic_bus_wrapper.v
set_top_module coreva_cpu_generic_bus_wrapper
read_sdc $ENTITY._default_constraint_mode_.sdc

if { [ file exists "$ENTITY.sdf" ] } {
read_sdf $ENTITY.sdf
} elseif { [ file exists "$ENTITY.Setup.sdf" ] } {
read_sdf $ENTITY.Setup.sdf
}

setDesignMode -process $::env(SOC_PROCESS)

# MULTI MODE MULTI CORNER (MMMC) SETUP
create_constraint_mode -name m_hold -sdc_files"$ENTITY._default_constraint_mode_.sdc"

#RC corners
create_library_set -name best_library_set -timing"$::env(SOC_MIN_TIMELIB)"
create_library_set -name worst_library_set -timing"$::env(SOC_MAX_TIMELIB)"
    
create_rc_corner -name rc_worst -qx_tech_file"$::env(SOC_QRCFILE_BEST)"
create_rc_corner -name rc_best  -qx_tech_file"$::env(SOC_QRCFILE_WORST)"
 
# OCV derating
create_delay_corner -name dc_setup -library_set {worst_library_set} -rc_corner {rc_worst}
create_delay_corner -name dc_hold -library_set {best_library_set} -rc_corner {rc_best}
   
create_analysis_view -name v_hold -constraint_mode {m_hold} -delay_corner {dc_hold}
create_analysis_view -name v_setup -constraint_mode {m_hold} -delay_corner {dc_setup}
 
setAnalysisMode -analysisType bcwc

We hope some can give us a kick in the right direction.

 Best regards,

Marten

 Dear All,

Can anyone tell me if Density screens are honored after optimization?  I'm trying to applyplacement density screens in EDI 14 but they

are not honored after optimization.

Thanks,

Aram

Hello,

In  the design I'm working on I have lot of small hold violations (~30ps) in the scan chains. The design is small, and the FFs in the scan chains are placed very close together. So the data path is very small and so the hold violations. 

Techno used is TSMC28nm (hold uncertainty is 50ps)

In have about 500 FFs and about 1000 hold buffers are added to fix these hold violations. I had a look to the library to see if there is a FF with a smaller hold time or  a big CKtoQ that could help but there is no.

The 1000 hold buffers added increase a lot the area of my design.

I tried to use the "useful skew" feature from EDI but the problem is that "useful skew" can be used only to fix setup violations from what I understood in the doc.

Do you have an idea on how to control the tool to force it using "useful skew" for hold fixing.

Do you have any other idea that could help?

Thanks in advance for your help.

Best regards

Chris