Hi all,
I am converting an already synthesized netlist to another technology using RTL compiler.. while doing this the generic netlist coud not generate a scan latch. It just reflects the same name in the generic netlist.
For scan flops we can unmap scan flops using, set_attribute unmap_scan_flops true . but for latches it doesn't apply...
so please share anything that makes this possilble.
Tanks
Hi,
I have a top module and child modules synthesized,when i am dumpng out netlist i only get the top modules,I assume it is a flat netlist.But i need the hierachical netlist ,I searched for the command but couldnt understand.Please specify with an example,if top.v is top file and 1.v 2.v 3.v are child modules ? then what is the command ??
Hello,
I am having an issue connecting to Bumps that is very strange and fairly random. Here are the symptoms:
1.) I have ~250 Bumps in my design. All except for 17 do not have an issue.
2.) I can clearly see the bump is assigned to the proper net. Bump label and info match the net name
3.) I can clearly see the net on M11 connecting to the Bump that is on M11
4.) EDI claims these nets are open...
I'm not sure what to do here. Has anyone seen this? Any advice on how to get the tool to pick up these routes?
Giuseppe
I have a doubt about CREATE BLACK BOX:
I have a testbench where I am trying to simulate two separate RTL designs that share some module names within their designs. I have tried compiling and elaborating them separately and then referencing their libraries but I still get error.
On Incisive Enterprise Simulator -> irun -> Elaboration Command Line Options -> Elaboration Command Line Options -> 1.2 ncelab Command options -> 1.2.20 -BBOX_Create directory have a example of how to create a Black Box, however I did all the steps of example 4 and did not work!!!!
print the following error:
irun -primname ip1 -bbox_link ./tmp/box1 -primname ip2 -bbox_link ./tmp/box2 soc.v
irun: 15.10-s002: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
irun: *E,DYNWKP: unable to locate the primary irun invocation from -PRIMNAME ip1.
irun: *E,DYNWKP: unable to locate the primary irun invocation from -PRIMNAME ip2.
irun: *E,DYNMPN: unable to locate primary snapshot from -PRIMNAME ip1.
Can you help me, about this?
Hi All,
I am new to PDN design. I am trying to create power Pads. I defined a MACRO with CLASS PAD, but I am not sure how to place it. Can someone please help me with a clear flow on how to do this?
Thanks.
It seems like old nets are kept in the database even if they are not in the new eco netlist. For example, I had a change that made this code:
DTC23 \otpData_o_reg[spare2][0] (.Q(\otpData_o[spare2] [0]),
.D(n_18),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][1] (.Q(\otpData_o[spare2] [1]),
.D(n_17),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][2] (.Q(\otpData_o[spare2] [2]),
.D(n_15),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][3] (.Q(\otpData_o[spare2] [3]),
.D(n_16),
.CLRZ(FE_OFN235_porZ),
.CLK(clkTrim17Lo));
Change to this:
DTC23 \otpData_o_reg[spare2][0] (.Q(NVM_TRACKER_SEL),
.D(n_18),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][1] (.Q(NVM_BOOST_DIS),
.D(n_17),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][2] (.Q(NVM_SYS_ALT_SEL),
.D(n_15),
.CLRZ(p4),
.CLK(clkTrim17Lo));
DTC23 \otpData_o_reg[spare2][3] (.Q(otpData_spare2_3),
.D(n_16),
.CLRZ(FE_OFN235_porZ),
.CLK(clkTrim17Lo));
So, I am only changing the output net to a new name. When I do this, Encounter takes the old names (i.e. \otpData_o[spare2] [0]) and defines internal wires for them like this:
wire \SPARE[19] ;
wire \SPARE[20] ;
wire \SPARE[21] ;
wire \\otpData_o[spare2] [0] ;
wire \\otpData_o[spare2] [1] ;
wire \\otpData_o[spare2] [2] ;
wire \\otpData_o[spare2] [3] ;
The “\\” is keeping the database from saving. I get this error when trying to save:
**ERROR: (ENCOAX-156): OA Exception : Input name (or member): \\otpData_o[spare2] [0] has improper bus syntax..
**ERROR: (ENCOAX-426): Error in creating EMH hierarchy.
TIMER: oaOut total process: 0h 0m 0.05s cpu {0h 0m 0s elapsed} Memory = 0.0
**ERROR: (ENCIMEX-7323): Could not save design into OA database.
Does anyone know a way to tell Encounter not to name it with \\ or how to remove the old physical wires from the database?? This is a postMask ECO, so I cannot re-synthesize.
Thanks!
Hi all,
I wonder whether it is possible to quickly open an schematic viewer to display a digital gates file
Given I have a .vg (or .v) file and a verilog gates libraries, is there any quick way to open an schematic browser via the command shell ? My only option at the moment is to call simvision and then, once there, send the design to the schematic viewer... Is there something faster, something like below:
$: simvision myfile.vg -y mylibs/tsmc18
Any comments welcome
Thanks
I have both stil and wgl files output by Tetramax. How do I use these as input to an ncsim simulation using irun?
Hi All,
We are seeing lots of M1 spacing erros despite having low placement density -- we bumped it down to even 30% placement density, but we still see lots of M1 spacing violations and ofcourse some shorts too.
We see around 2k M1 violations, 200 M2 violations, and none in M3,M4 and M5 -- my doubt is why it didnt use higher metals to route, and resolve DRCs in M1/M2 when lots of area is available.
Also, would like to input that, at some places, the M1 net is routed so close to the M1 std cell pin, as if the router doesnt see the pins, or doesnt recognize the std cell lef properly.
BTW, we are trying to use this new fab and library for first time in 180nm , so there is a possiblity that the tech.lef or the std cell lef could contain errors too -- plz point me if there is a way to validate them.
Thans a lot for your help .
Thanks,
Raj.
Hi all,
After doing sroute for pad pins only, the connectivity report gives the following violations:
Net VCC, Pin VDD_PAD.VCC: unconnected terminal at (696.070000,1633.320000) (732.870000,1636.800000)
Net VCC: special open at (265.350000,265.350000) (1371.450000,1423.350000)
Net GND, Pin VSS_PAD.GND: unconnected terminal at (696.070000,0.000000) (732.870000,3.480000)
Net GND: special open at (273.960000,213.250000) (1362.840000,1361.240000)
Where: VDD_PAD: is the VDD pad, and the pin VCC is the only pin defined for it in the lef. The same for VSS_PAD.
My lef power, ground pins either for standard cells or core power pads is VCC, and GND, and also I defined my global nets in encounter to be the same names.
I used those commands for global connect:
globalNetConnect VCC -type pgpin -pin VCC -inst *
globalNetConnect VCC -type net -net VCC
globalNetConnect VCC -type tiehi
globalNetConnect GND -type pgpin -pin GND -inst *
globalNetConnect GND -type net -net GND
globalNetConnect GND -type tielo
My thoughts tell me that I can ignore the unconnected terminals warnings, because it will be connected using i/o filler cells to complete the power ring for pads.
Attached is a pic. for my chip with violation markers.
Any help how can I solve this !
Thanks you.
AbdUllah,
We would like to do this post-mask. So we have a routed design and we simply want to add and delete top-level IO pins.
How do we add and delete IO ports in Encounter?
Original:
module top ( A, B, C );
macro1 U_macro1 (.A(A), .B(B), .C(C) );
New:
module top (A,C,New);
macro1 U_macro1 (.A(A), .C(C), .New(New);
So B has been deleted and New has been added
I would want to know which cells(an inv/buf pair or inv only or buf only) used for Clock tree synthesis is better for the designs in terms of latency, skew , slew and power!
It may not be a one size fits all solution but i would want to build better clocks.
Hi All,
I am trying to read in the constraints which contain create clock commands,and then try the createClkTreeSpec command with alist of usable buffers and inverters.
However it does dump out a file with exclude points, dont touch nets etc., but doenst dump out the clock tree root pins definitions.
Can some one point me what I might be doing wrong.
Thanks,
Rajesh.
Hello,
Is there a way to force Encounter 14.2 to rename all upper case net or cell names to the lower case? Or maybe I could just rename the specific nets one by one as an ECO?
Actually, I am looking for something similar to DC commands:
define_name_rules case_insensitive_net -type net -allowed "a-z 0-9_*"
define_name_rules case_insensitive_cell -type cell -allowed "a-z 0-9_*"
change_names -verbose -rules case_insensitive_net -hierarchy
change_names -verbose -rules case_insensitive_cell -hierarchy
Thanks!
Boris
Hello,
I am having an issue connecting to Bumps that is very strange and fairly random. Here are the symptoms:
1.) I have ~250 Bumps in my design. All except for 17 do not have an issue.
2.) I can clearly see the bump is assigned to the proper net. Bump label and info match the net name
3.) I can clearly see the net on M11 connecting to the Bump that is on M11
4.) EDI claims these nets are open...
I'm not sure what to do here. Has anyone seen this? Any advice on how to get the tool to pick up these routes?
Giuseppe
Hello everyone,
I'm trying to use the sign-off option available in EDI for optimization and also timing report. Everything goes well till after post route stage, however I somehow trapped in an iterative loop which cannot get out!
After setting the RC Extraction mode to be in sign-off level (coupled true) and having the timing analysis mode with OCV ( Delay Calculation Options: engine=aae signOff=true SIAware=true(signoff)).
During optimization I encounter:
**ERROR: (ENCOPT-7055): use setDelayCalMode -engine [feDC | signalStorm] -SIAware false before running optDesign -postRoute -signoff.
and when I want to get a timing report I get the following:
"ERROR: (ENCESI-2017): There is no coupling capacitance found in the design. Use setDelayCalMode -siAware false to perform base delay analysis. SI analysis requires the parasitics database to contain coupling capacitance. To perform SI analysis, use 'setExtractRCMode -coupled true' prior to extraction or load a SPEF with coupling capacitance and re-run."
the last one is a bit confusing since I already set the -coupled option to be true and it works fine in post route stage (without sign off option). Any idea where is the problem?
Regards,
Meysam
Hi all,
I am loading a design in innovus by following commands and it is working fine
source xyz.globals
init_design
but when i do it in older version of encounter while readding tech lef the below error messages are coming.i need a fix to this problem,
Loading LEF file pqrs.lef...
ERROR (LEFPARS-1505): MANUFACTURINGGRID statement was defined before UNITS.
Refer the LEF Language Reference manual for the order of LEF statements. Error in file pqrs.lef at line 22, on token UNITS.
**ERROR: (ENCLF-3): Error found when processing LEF file 'pqrs.lef'. The subsequent file content is ignored. Refer to error messages above for details. Fix the errors, and restart 'Encounter' again.
Type 'man ENCLF-3' for more detail.
encounter 12> **ERROR: **ERROR: (ENCSYT-16013): Loading LEF file(s) failed, and has aborted. Refer to error messages above for details. Fix the errors, and restart again.
why it is showing syntax error ??
Hi,
I am trying to generate .lib file for CELEMENT. So, I need to generate functionality which also have Z-state.
But when I identify the gate then its functionality is fine. But When I generate .alf file using generated spec file then I not getting any transistion on timing part.
I am not getting any transition like 0---Z or 1----Z.
Gate Identification: See Figure
See Figure for spec file .....
So, with this spec file I am not getting the timing delay for output 0---Z or 1--Z transition,
Thanks,
Hemal
Hello all,
I have the following queries regarding the use of set_dont_touch_network on the clock net.
1. Should set_dont_touch_network be used on clock during synthesis in Genus ? ( to prevent optimization in clock network )
2. If set_dont_touch_network is used during synthesis, it gets written out into the sdc file. Will this affect the clock tree synthesis in Innovus?
What is the usual procedure followed in this respect?
Thanks,
Chithra
Lately I have been spending more of my time in the Genus virtual world than my normal Innovus reality .
One procedure that stands out in Genus application notes reports 'every single non default' environmental variable from the current run.
proc all_nondefault_root_attrs {} { puts "\n[string repeat "-" 40]"
puts "non-default root attributes" puts "[string repeat "-" 40]"
foreach a [lsort [find /object_types/root -attr *]] { set attr [basename $a]
redirect /dev/null {set val [get_attr $attr /]}
set def [get_attr default_value $a] if {$val ne $def} { puts " $attr = $val" } } puts "[string repeat "-" 40]\n" }
all_nondefault_root_attrs
This style of report would be incredibly useful in Innovus , especially if it understood the "Auto-tune" features of the smaller nodes.
Shawn