Hi,
I compare RTl vs RTL using con-formal. I created black box for IP in RTL and I did mapping but few signals are not mapped due to different name. How to change "pin name" of black box.
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command for renaming pin name of blackbox
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Is it possible to import and simulate in virtuoso without the exact GDS info of the layout??
Hello everyone,
For the standard cell library I was provided with, I have the following files:
1. .lib files(worst,best,typ etc.) 2. .v file (verilog description of the std cell library) 3. .lef file 4. captable
With these files I was successfully able to do:
1. RTL synthesis (done by Genus) 2. PnR using innovus (including postroute optimization)
Now I want to import the design in virtuoso and run rc extraction, simulations etc. But I have no GDS file of the standard cells. Instead, I was given some phantom views (FRAM view, CEL view etc.) which are some sort of abstract views (please correct me if I am wrong) supported by synopsys as I have come to learn and I do not have the tool. All I can generate is the GDS of the routing info from innovus. Now, please tell me how far I can go with these.
I am still learning the tools. And I found out that it is possible to create abstract views of the standard cells using .lef file from innovus.
I was wondering if it is possible to import and run simulation from virtuoso using these abstract views?
I still have no idea how the rc extraction can be done using this information. But while doing the PnR, innovus uses the RC extract information and optimizes thereby. So the information is available for innovus in .lib files and captables. Is it possbile to import this info to virtuoso in some way and run the simulations from there??
I should also add that I have the PDK using which the standard cells were created. But without the exact GDS information, will it be of any help??
Please correct me if I am missing something obvious. Any kind of help, suggestion will be very much appreciated. Thanks in advance.
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Macro Placement Issue with Custom LEF file
Hi all,
I have a macro that is essentially a special-via (two metal layers connected through a cut layer). My netlist includes several of these macros as physical-only cells defined in a LEF file with the following class
CLASS BLOCK ;
PROPERTY LEF58_CLASS "CLASS COVER FILL ; " ;
I want to place and route the design with these cells in it. Since they are metal-only I want the tool to place them on top of the normal cells and place them in an optimal for delay and congestion position. In the design if I use the standard cell placement to place these macros, it will ignore the blockage in the macros and place them on top of one another. So I use the macroPlacer (planDesign) to preplace them. Using the medium effort it will place them in an array disregarding their proximity to the cells/nets they connect to. If I use the high effort option, it seems to ignore my macroSpacing and minMacrotoCore constraints and keeps placing some outside the core or too close to one another.
I have used various LEF classes, various planDesign constraints, and various planDesign options, using Halos and etc., and nothing seems to work perfectly. Why can't the tool simply understand that there is an internal blockage in the macro on metal 2 and 3 and place them accordingly?
Is there any way to improve upon this situation? :-(
Bests,
Kaveh
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Auto complete tab not work
Dear All,
There are some pre-defined procs that I could not use tab to auto complete, but some procs can work. I used innovus shell prompt.
Could anyone tell me why and how to use them normally? Thanks in advance!
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NCVLOG error NPITEM -- Not a valid package item: 'interface_declaration' [SystemVerilog]
Hi,
I am trying to compile a design with Incisive, using "irun" commands.
The design was previously compiled and tested with VCS.
When compiling some VIPs, I encountered multiple times the following error:
- Not a valid package item: 'interface_declaration' [SystemVerilog]
In particular it seems related to the declaration of "interface class name" inside the code.
I could not find anything related to this problem and it prevents the compilation to succeed.
The swithces I am currently using are " -elaborate -sv -64bit -uvmhome CDNS-1.2"
Thanks in advance for any help.
Luca
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Compilation Errors for UVM constructs using xcelium
Hi,
I will shortyly tell the problem:
The following code line :
if(!$cast(tmp,rhs))
`uvm_fatal(get_type_name().toupper(), "Type mismatch")
|
Generates two different errors at compile time :
*E,FCBLTIN ... built-in method call following a function call is not generally supported.
*E,NOTFXX ... Expecting a function name [10.3.3(IEEE)].
I cannot find out why this is not working.
Thanks in advance for the help,
Luca
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SRAM Design
I am designing a SRAM cell in 45nm technology. For reading and writing i am designing the complete circuit using a precharge, write driver and sense amplifier. When I an activating the precharge circuit bit lines are not pulling upto supply vdd. Can anyone help me regarding this problem?
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Placement algorithm that used in SOC Encounter
Hi all,
I am relatively new to the Encounter tool. I am using Encounter v6.2 to place a simple design.
I have a question about the Place & Route Algorithm that used in this software.
I want to know, does this algorithm deterministic? that means any times will make the same result for the same input netlist or not? is not any solution to get the same result?
Thanks a lot, Amir
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Static Rail Analysis Problem
Hello,
I am doing a static rail analysis for a small design. I am getting a following error and warning in-spite of properly defining the proper power pin, power net, ground pin and ground net:
Analyze Rail Settings:
Temp directory: /tmp/ssv_tmpdir_161280_bh1R11
Output directory: /home/suhas/Desktop/genus_invs_des/staticRailResults
Run directory: /home/suhas/Desktop/genus_invs_des/staticRailResults/ALL_0C_avg_8/
Begin Merging Power Grid for net VSS
** WARN: (VOLTUS_RAIL-4022): The cell type "macro" didn't match any cell in cell libraries.
** WARN: (VOLTUS_RAIL-4022): The cell type "io" didn't match any cell in cell libraries.
** WARN: (VOLTUS_RAIL-4016): No interface node connections present in top-level PGDB.
Merging cell power views for net VSS
Merged power views for 0 cells
Processed 0 cell internal tap current sources.
Processed 0 cell internal resistors.
EM: 0 IR: 0 Early: 0 Tech: 0 Unused: 1
** WARN: (VOLTUS_RAIL-4065): The following 1 cells do not have connection from
the power pins to the global grid VSS, no powergrid library will be used.
AND
Ended Merging Power Grid for net VSS: (cpu=0:00:01, real=0:00:02, mem(process/total)=40.28MB/758.92MB)
Merge Grid Statistics:
VSS: 0 cells
EM: 0 IR: 0 Early: 0 Tech: 0 Unused: 1
Begin Merging Power Grid for net VDD
** WARN: (VOLTUS_RAIL-4076): The net VDD is marked as incomplete net
Merge Grid Statistics:
** WARN: (VOLTUS_RAIL-2091): Found incomplete net, VSS, it will be skipped in the analysis and the report.
** WARN: (VOLTUS_RAIL-2091): Found incomplete net, VDD, it will be skipped in the analysis and the report.
** ERROR: (VOLTUS_RAIL-1259): Failed to run domain based rail analysis - required at least one power net and one ground net. Only 0 nets () found, the other nets (VSS, VDD) are incomplete.
*** Error: In processing command script
Rail Analysis failed.
1 error was found while processing the file /tmp/ssv_tmpdir_161280_bh1R11/voltus_rail_161280.cmd
Rail Analysis Statistics:
Warning messages: 5
Error messages: 2
Rail Analysis is unsuccessful due to errors.
Finished Rail Analysis at 12:29:33 09/18/2017 (cpu=0:00:02, real=0:00:05, peak mem=758.92MB)
Current Voltus IC Power Integrity Solution resource usage: (total cpu=0:00:21, real=0:01:10, mem=718.73MB)
voltus_rail exited unsuccessfully.
**ERROR: (PRL-387): "Rail Analysis" failed to finish successfully.
Please let me know where I am going wrong, the design is a small AND gate power and rail analysis.
Regards
Suhas.S
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GPDK045: QRC Extraction fails with Innovus v16.13-s045_1
Hello,
I am using the GPDK045, but Innovus segfaults upon RC extraction. Maybe I have set up something wrong?
My RC Corner is:
create_rc_corner -name rc_corner\
-cap_table {GPDK045/gpdk045_v_5_0/soce/gpdk045.extended.CapTbl}\
-qx_tech_file {GPDK045/gsclib045_all_v4.4/gsclib045/qrc/qx/gpdk045.tch}
My flow always segfaults during "routeDesign" when the RC extraction runs. Both tQuantus and iQuantus segfault with the above RC corner setup.
Can someone help me out here please or reproduce the problem?
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Innovus Common UI
Hello There!
Just a very brief question. There is a very nice command in Genus to report runtime and memory usage - "time_info". I am looking for something similar for Innovus ( common ui ).
Thanks and best regards,
Boris
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Metal-layer Cells
Hi All,
I have special devices that similar to vias lie between two metal layers (think about a metal-insulator-metal capacitor, a metal-to-metal fuse, or a component similar to that). The device is completely on metal layers so it can and should be placed on top of cells but it has blockages and pins that need to be considered.
Is there a flow for having the place and route engine place these elements and route them automatically. I have tried the following approach with no luck:
I created the cell in Virtuoso and got the abstract generator to give me a LEF file for it. Then I played with the LEF macro type (block, cover, bump, etc.). Then used the automatic floorplanning capabilities in Encounter to place the Macros across the design and then routed them. I went through all sorts of placement and LEF cell variations none seemed to give me good results (placing the macros on top of each other ignoring the blockage, or placing them without considering proximity, or placing them outside the core boundaries).
I can't help but think that there is a standard flow for placing and routing such elements. Perhaps defining CustomVias? The device is very similar to a Via but it has to be inserted in the netslist as a cell rather than some technology construct. Any help will be appreciated.
Thanks,
Kaveh
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ccopt ignore sink - common ui
Hello,
I am looking for a way to remove several sink points from the list of CCOPT leafs, to make sure it will not build the clock tree to these pins.
Thanks and regards,
Boris
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Core filler not getting inserted below vertical power stripe
I am using Innovus Implementation system V15.20 for my design flow,
My design contains custom made cells for which lib and lef file has been generated manually (using liberate and abstarct tool respectively),
During the backend flow, when I'm trying to insert core filler in the post routed design. I see that the core filler is not inserted below the vertical
power stripes which is causing DRC violations in the design.
Please help me fix this.
The picture of filler cell not inserted in the design is attached and the command used for filler cell insertion is :
addFiller -cell feedth9 -prefix FILLER -doDRC
addFiller -cell feedth3 -prefix FILLER -doDRC
addFiller -cell feedth -prefix FILLER -doDRC
Thanks in advance.
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Missing libraries when running Innovus Clock Tree Synthesis
Hello,
I'm running innovus 16.2 on Linux Centos 6.
I've got a problem at clock synthesis stage when instanciating buffer and etc ... It prints the message :
**ERROR: (IMPCCOPT-3092): Couldn't load external LP solver library. Error returned:
libCDSCoinUtils.so: cannot open shared object file: No such file or directory
libCoinUtils.so: cannot open shared object file: No such file or directory
libCDSClp.so: cannot open shared object file: No such file or directory
libClp.so: cannot open shared object file: No such file or directory.
So it is not linking. Does anyone know that problem? Do you know what package I need to install?
Regards,
Remi
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Level-shifter cells are removed after placement
Hi there!
In my design, I intend to have a power domain containing all level-shifter cells.
The steps I have taken towards this target:
1- using a clock buffer as the level-shifter component in LevelShiftDomain.vhd
2- synthesizing the design
3- CPF file containing all necessary details, such as powerDomains and their definition, all available level-shifter cells to use (define_level_shifter_cell) and rule to use them (create_level_shifter_rule)
however after place_design, cells from level-shifter power domain are removed.
What is your suggestion to solve this issue?
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I/O pad pins are placed randomly (each pad_pin is not placed on the corresponding pad)
Hi all,
in Innovus 16.2, after "init_design", the I/O pads' terminals are not placed on the corresponding pad. Does anybody have had similar problems? or any clue about this?
As you can see in the screenshot, there are 3 yellow triangles (pad's terminal). the 2 at left side are placed correctly ON THE PAD. however, the third one at the right side is placed ABOVE THE PAD.
This problem occurs after "init_design". the pads settings are the same, but some of pads' terminals are placed randomly.
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tie cell net connection missing
Why Tie Cell connections are missing in the instantiated module in the final PNR Verilog netlist, Module declaration in the final netlist has tie cell connections but the instantiated cell doesn't show tie connections.
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Generating ITF file from ICT file?
Building a new flow that involves StarRC and wanted to understand if there was any recommendations of converting an ICT file into the ITF files using as the source for StarRC's reference files? From the ITF file I can generate the rest that is required.
Thanks,
TomT...
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CPF - two primary_power_nets for one power domain (different virtual power domains for different voltage sites of an IP block)
Hi there!
Cadence innovus 16.13 | CPF v1.1 | ST Microelectronic 28nm
I am working on a Multiple power domain design. I have got a PLL block as an IP (no access inside the block of course) and this PLL block according to its vendor datasheet consists of two separate domain:
- an internal analog part with 1.8V
- an internal digital part with 0.9
I need to put this whole IP block in one domain for instance PD_PLL. However, since there are two separate analog and digital parts in the IP block, no update_power_domain -primary_power_net can be used for the whole PD_PLL. Therefore, I used two virtual power domain in my CPF file. This is an excerpt of the whole lines of CPF file:
- define_library_set -name lib_0_80V_12t_lvt_lp_tc -libraries AND ALL OTHER LIBRARY SETS
- define_level_shifter_cell ALL NECESSARY CELLS
- create_power_nets -nets {VDD_LEVELSHIFT} -voltage 0.80:1.20
- create_power_nets -nets {AVDD_PLL} -voltage 1.8
- create_power_nets -nets {DVDD_PLL} -voltage 0.9
- AND ALL OTHER NETS ...
- create_power_domain -name PD_PLL -instances ...
- create_power_domain -name PD_LEVELSHIFT -instances ...
- # Creating virtual power Domain for analog and digital parts of PLL to assign primary power_nets
- create_power_domain -name PD_DPLL
- create_power_domain -name PD_APLL
- create_level_shifter_rule -name lsr_pad_pllout -pins {ChipTop_1/LevelShiftDomain_1/INFOUT*} -from PD_DPLL -to PD_LEVELSHIFT
- update_level_shifter_rules -names lsr_pad_pllout -location to
- create_nominal_condition -name cond_high_lvt_lp_12t_0v80 -voltage 0.80
- update_nominal_condition -name cond_high_lvt_lp_12t_0v80 -library_set "lib_0_80V_12t_lvt_lp_tc"
- and for all other voltages
- create_power_mode -name PM_0v80 -domain_conditions {PD_SRAM0@cond_high_lvt_lp_12t_0v80 \
- create_global_connection
- create_global_connection -domain PD_PLL -net AVDD_PLL -pins avddpll1v8
- create_global_connection -domain PD_PLL -net AGND_PLL -pins agndpll1v8
- create_global_connection -domain PD_PLL -net DVDD_PLL -pins dvddpll0v9
- create_global_connection -domain PD_PLL -net DGND_PLL -pins dgndpll0v9
- update_power_domain -name PD_DEFAULT -primary_power_net VDD_DEFAULT -primary_ground_net GND -pmos_bias_net VDDS_LVT -nmos_bias_net GNDS_LVT
- # update virtual power domains for PLL
- update_power_domain -name PD_DPLL -primary_power_net DVDD_PLL -primary_ground_net DGND_PLL
- update_power_domain -name PD_APLL -primary_power_net AVDD_PLL -primary_ground_net AGND_PLL
The problem happens when I want to transfer signals from 0.90V section to a levelshifter for voltage upscaling. after commiting the CPF file, the following come from CPF commit generated report:
**WARN: (IMPCPF-2204): Cannot get the primary power net for the power domain PD_PLL, using first power net DVDD_PLL specified in connections as primary power net.
**ERROR: (IMPCPF-261): line 735: create_level_shifter_rule lsr_pad_pllout: Cannot insert a level shifter instance to drive a net from power domain PD_DPLL to power domain PD_LEVELSHIFT, with a valid location in power domain to. The valid cell for this rule was not found. Ensure that the location specified in update_level_shifter_rule is identical to the 'valid_location' option specified by define_level_shifter command.
How I can assign two separate power domains to different voltage sites in an IP block and later assign them their respective primary_power_nets and avoiding any problem like the above which doesnt let the tool to add the necessary level shifter cells in PD_LEVELSHIFT for upscaling the signals coming from 0.90V part.
Regards
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