Hello,

According to ieee.1364 9.2.1:
“A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1)”
and 9.2.2:
“The nonblocking procedural assignment allows assignment scheduling without blocking the procedural flow.”

The basic is that for blocking =, compiler calculate a dependency graph first, then simplify to combinational logic; for => it is simultaneous assignment.
Just as ieee C++ spec doesn’t stipulate how virtual table is to laid out (as there are IA64 and MSVC ways to do that), the 1364 spec lacks further restrictions.
1) Conflict: if Reg A is being assigned in an always block in both categories
   a. First among blocking =’s, then among =>’s, how to resolve?
   b. First among =>’s, then =’s, how?

I know that for a) case, Quartus basically accept that, but would prohibit any further blocking assignment. How does Cadence tools treat this?
2) There is a question that for 9.2.1 =’s, because it is defined to be sequential, it somehow suggest the existence of clocks, and indeed #n delay can be added for simulation, and in fact some document suggest that maybe a decade ago there were tools also adding clock delays for #n into synthesis, but that requires knowledge of the specific clock design. I could not find definitive clarification in IEEE standards on this. If, for some ill-define =’s statements, assignment for registers unavoidably require adding delay to ensure correctness, how does Cadence NC tools treat them? Does Cadence conform to any standards in doing that?

Regardfs,
G

Pretty much the title, I have a requirement of getting the layer wise parasitic information. Is there a utility or an option in the gui that allows me to get extraction for specific nets or specific layers?

Thanks a ton, this community has been really helpful.

Hello,

I have multiple (6) power domains in my design. I am placing stripes using the addStripe command but every time I am ending up with a design in which the rails are extending outside the selected power domain. Please see attached screenshot.

To resolve the issue, I have tried most of the options, like using -over_power_domain, area {x1 y1 x2 y2} etc. Please see my below code

modifyPowerDomainAttr PD_1 -box 24 44 56 76 -gapEdges {20 20 20 20}
selectObject Group PD_1
addStripe -max_same_layer_jog_length 8 \
-stop_x 56 \
-stop_y 76 \
-width 4 \
-over_power_domain 1 \
-nets VDD_CORE1 \
-start_x 24 \
-start_y 44 \
-set_to_set_distance 5 \
-spacing 1 \
-merge_stripes_value 0.068 \
-layer M2 \

The screenshot shows the PD_1 power domain in which you can see VDD_CORE1 extending over and above the power domain which is not what I want.

Apart from this last used code, I have used other variations but end up in which the VDD_CORE1 (the power rail in this case) extends over the entire design. Other times, the entire design is flooded. Please assist me in this and let me know where I maybe going wrong.

Thanks,
Kashif

Hello,

I am trying to build a hierarchical design using Innovus, but I have a problem with closing the timing.

My design is composed by different clone and master blocks. I partition the design and I do the block level implementation for each master partition. From the block level implementation I generate DEF, LIB and LEF files, along with the netlist (.v file) of each master partition. I manage to fix the timing in each partition. The problem comes when I am trying to close the timing on the top level. I am using the LIB and LEF files to create the layout and do the clock tree synthesis and Routing. Up to the point before I assemble the design everything looks to be ok. After I assemble the design the timing breaks down. One issue that I notice, is that the clock used after assembling the design, when I do the timing analysis, is the ideal clock. I use the update_clock_latencies command to get the actual clock and that is when the timing gets violated.

I have also used the set_propagate_clock command in my constraints when importing the top design. That solved the ideal clock problem (now i am getting propagated clock), but the overall timing violation issue remained. Meaning that before assembling the design everything works as expected and the timing is met. After I assemble the design the timing gets violated.

I am sorry if the question is kind of stupid, my experience is limited. Any help would be greatly appreciated.

Best Regards,

Dimitrios

Hello,

I am using multiple power domains in my design and while doing the routing of power structures (using the -sroute command), I see that the VDD_CORE1 wire (in my case) always extends by a small margin beyond the power domain. Before running the sroute command, I use the modifyPowerDomainAttr commad to adjust the size of the power domain so that it sits exactly on top of the power rail I want to route. And then I use the sroute command.

But I keep getting this "dangling" wires which is leading to further DRC errors; also sometimes for the global PWR rails, the routing is incomplete leaving the nets unconnected.

Please assist me in this.  I am attaching a screenshot of the issue and the command I am using.

modifyPowerDomainAttr PD_1 -box 188 238 262 312 -minGaps {4 4 4 4}   // adjustPower domain to accommodate the VDD_CORE1 rail exactly

sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { M1(1) LB(9) } -blockPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd }  -allowJogging 1 -powerDomains { PD_1 } -crossoverViaLayerRange { M1(1) LB(9) } -nets { GND } -allowLayerChange 1 -targetViaLayerRange { M1(1) LB(9) }

modifyPowerDomainAttr PD_1 -box 200 250 250 300 -minGaps {4 4 4 4}  // re-adjust back to original

Thanks,
Kashif

Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.

How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any  clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ? 

thank you for  your time. 

From all the documentation that I see, it looks like "common timing library" in encounter's "import design" menu should point to the typical case library. Similarly to how the "max" and "min" libraries point to the worst and best case libraries. 

However, when I look at the log, it says that its overwriting the libraries. See below. 

Reading max timing library <my_wc_timing_lib>

................etc

Reading min timing library <my_bc_timing_lib>

................etc

Reading max timing library <my_tc_timing_lib> 

................etc

Reading min timing library <my_tc_timing_lib> 

................etc

Those last two messages seem to indicate the reading in of the common-timing library is over-writing my max and min timing libraries. Is this correct? Is this what I should see? 

Thanks

Matt 

Hi,

Using the hierarchical partitioning flow, I want to create an individual power domain for each partition, which can be turned off. 
I've been reading the Innovus user guide "Multiple Supply Voltage Top-Down Hierarchical Flow", but it is rather vague.

As specified I've used 'savePartition' to generate CPF files for each block and for the top-level design.
In the Block-Level CPF Generation chapter, the following is mentioned; "Creates the power domains referenced by the block-level CPF files", weird how it refers to block-level CPF while generating the block-level.

Secondly, in the Top-Level CPF Generation chapter, the following is mentioned "Defines each block-level boundary power domain information through create_power_domain -boundary_ports." generated from the chip-level CPF. However, the generated top-level do not contain these definitions.

Hence the question, how should the chip-level CPF be defined? Currently, I create power domains for each partition after 'definePartition' using read_power_intent/commit_power_intent followed by timing budgeting and partitioning. The block-level CPF generated for a partition contains only the default power-domain, which is not as expected since a different power-domain was specified for the partition (I.e. the partition does not have the right globalConnection)

Thanks.

We know, through jogging higher metal layer antenna rules violation could be solved (most of the case).

When I import my gds , there are some antenna violation which could be solved  through jogging through higher metal layer (there is M2-M3-M2-M3 connection, but if it was M2-M3-M4-M3 , there should be no antenna violation). How could I manage this type of mistakes ? 

side-note: I have no antenna cell , so I have to solve my antenna through jogging.

I am using this function however I am unable to check basic errors like missing signal in sensitivity list.

What can I do now? 

hal -V93 -GUI -nowarn MAXLEN -nowarn CTLCHR -nowarn IDLENG -nowarn NUMSUF -nowarn UCCONN ./myvhdl.vhd -top myvhdl_top

Version is, 

hal: 15.10-s010: (c) Copyright 1995-2015 Cadence Design Systems, Inc.

Thank you!

Hello,

Is there a way to extract the placement information of the gates (like in X Y coordinates)in soc Encounter?

I would use this information to know the neighboring pair of gates throughout my design.

Thankyou.

In my design, I have a clock generation block which generate main clock pulse ( no external clock reference is used like PLL ) . I'm facing problem defining sdc clock description.

I've tried; "create_clock" & "create_generated_clock" both command, but it fails to create any clock tree definition.

**WARN: (IMPCCOPT-4144):    The SDC clock func has source pin clk, which is an input pin. Clock trees for this clock will be defined under the corresponding output pins instead.
Type 'man IMPCCOPT-4144' for more detail.
Analyzing clock structure done.
Checking clock tree convergence...
Checking clock tree convergence done.
Placement constraints of type 'region' or 'fence' will not be downgraded to 'guide' because the property change_fences_to_guides has been set to false.
Set place::cacheFPlanSiteMark to 1
**ERROR: (IMPCCOPT-2004):    Cannot run 'CCOpt' as no clock trees are defined.
**ERROR: (IMPCCOPT-2196):    Cannot run ccopt_design because the command prerequisites were not met. Review the previous error messages for more details about the failure.

How can I approach to handle this situation?

I may have some misunderstanding about this whole thing and how to approach. Any example or source would be appreciable.

Hi,

I want to execute global routing and export the global routing output in a file, probably a .guide file such as the ones in the benchmarks of ISPD 2018 Contest (http://www.ispd.cc/contests/18/index.htm).

By global routing output I mean the sets of rectangles that act as guides for each net in detailed routing.

I am currently using Innovus tool and I didnt find the option to do it. The closest I've found is to execute Early Global Routing and then using the "saveRouteGuide" command, but this seems to be a pre-step of global routing.

My design block macro have a pin to be connected to bump directly at the top level ( I want

the P&R person to place a bump at the center of that pin). According to EDI system user guide,

the PORT definition will be enhanced to have a CLASS BUMP associated to it. But I don't know how

to get that statement when I create LEF from abstract generator ? Or I just hand-edit the LEF file ?

for example :

Macro myblock

   CLASS BLOCK;

   SIZE 2661 BY 696;

   ORIGIN 0 0;

   SYMMETRY X Y R90;

   PIN A1

      DIRECTION OUTPUT;

      USE SIGNAL;

      PORT

         CLASS BUMP;

          LAYER AP;

          RECT 2469 0 2490 83;

     END

Thanks for help

I am having a lot of difficulty with a flip chip Area IO design. In the design, the IO cell with pin PAD is connected to a BUMP using fcRoute (wide top level metal, low resistance). When I run report_annotated_parasitics command I can see all of my real nets are annotated except for the 131 bi-directional top level nets connected PAD to BUMP. Is there a way to debug why these nets are not annotated? 

Hello,

I have somme issues with Veriffy Connectivity on Soc Encounter. Actually when I run veriffy connectivity I have somme violations on pad rings (ring_VDD and ring_GND) as Open.

I do the connect global net as following:

======================================
globalNetConnect ring_VDD -type pgpin -pin {vdd} -all -override -verbose
globalNetConnect ring_GND -type pgpin -pin {gnd} -all -override -verbose
globalNetConnect ring_GND -type tielo -all -override -verbose
globalNetConnect ring_VDD -type tiehi -all -override -verbose
globalNetConnect ring_VDD -type pgpin -pin {VDD} -all -override -verbose
globalNetConnect ring_VDDE -type pgpin -pin {VDDE} -all -override -verbose
globalNetConnect ring_GND -type pgpin -pin {GND} -all -override -verbose
globalNetConnect ring_GNDE -type pgpin -pin {GNDE} -all -override -verbose
globalNetConnect ring_A0SRC -type pgpin -pin {A0SRC} -all -override -verbose
globalNetConnect ring_A1SRC -type pgpin -pin {A1SRC} -all -override -verbose
globalNetConnect ring_A2SRC -type pgpin -pin {A2SRC} -all -override -verbose
globalNetConnect ring_A3SRC -type pgpin -pin {A3SRC} -all -override -verbose
globalNetConnect ring_A4SRC -type pgpin -pin {A4SRC} -all -override -verbose
globalNetConnect ring_A5SRC -type pgpin -pin {A5SRC} -all -override -verbose
globalNetConnect ring_A6SRC -type pgpin -pin {A6SRC} -all -override -verbose  
globalNetConnect ring_TRIGGER -type pgpin -pin {TRIGGER} -all -override -verbose
globalNetConnect ring_BOOST -type pgpin -pin {BOOST} -all -override -verbose
globalNetConnect ring_REFIO -type pgpin -pin {REFIO} -all -override -verbose

do you have somme ideas on these violation and Can you pleas help me to fix these.

Thank you

Hello,

when I am doing nanoroute with soc encounter, i have my I/O nets not routed to the PADs Pins but when I do veriffy connectivity, I don't have violations in these I/O nets.

When I check the wires of the I/O net, they are not routed to the pin pad and just stop routing near from it.

does anyone has an ideas why nanoroute does not route the I/O net to pads and how I can fix that.

Thank you for your response,

Bilal,

Ps: With Trial route the I/Os net are routes to the Pins Pads.

Dear all,

I'm trying to benefit from OA interoperability between Innovus and Cadence IC (Virtuoso) environments for a digital-on-top mixed-signal design. In short, during floorplan I would like to import into Innovus the pre-placement of some analog macros as prepared into the Virtuoso environment. I know that this can be done with the oaIn command,

oaIn libName cellName viewName [-filter {block_insts blockages boundary fixed_core_insts floorplan pad_insts pin_shapes regions regular_routing special_routing}] [-net { netnames }]

This works out-of-the-box only for a flat design in which analog macros are instantiated at top-level, e.g. top/PLL_INST etc.

Indeed, in my case an additional level of logical design hierarchy is part of the design e.g. top/analog/PLL_INST and we cannot flatten the design hierarchy. With this configuration the oaIn command doesn't work anymore, because the analog macro top/analog/PLL_INST in the Verilog gate-level netlist is not found in the corresponding layout view, which instantiates just a PLL design with instance name PLL_INST.

I tried to build with OA layout views a physical hierarchy reflecting the same logical hierarchy I need, i.e. I created a top-level floorplan layout top, instantiating an analog layout that further instantiates the PLL block with instance name PLL_INST but oaIn run on this doesn't recognise the PLL_INST anymore.

Is there the possibility to hierarchical import instances placement from OA into Innovus ?

p.s. I alredy well know that I can place all my instances with the placeInstance command, but in this way any change done in the OA placement would automatically reflect in Innovus, which is faster since I have more than 50 analog macros to place in the design.

Regard

Luca

Hello,

Could you please layout the details, how to simulate a fully differential output buffer(Tx) and fully differential input buffer(Rx) ibis model in Virtuoso?!

The ibis buffer from analogLib is not working in differential mode. Beside there are no options to specify the io signal type (e.g. if the signal io is P/N type). Also I could not specify the Pin number!

Only the Model name is not sufficient in my case. I wish to declare the pin number and type of signal along with the model name such that the io buffer could identify the target model distinctly within the XXX.ibs file. Kindly give your suggestion ASAP.

Regards,

Bitan
Virtuoso Version: 6.1.6-64b

Simulator: Specter

Dear all,

I'm using Innovus to P&R a design consisting of custom made cells. The cells have been characterized and compiled into a .lib file using Synopsys SiliconSmart.
Everything works as expected, but I cannot do clock synthesis as Innovus does not detect my inverters as usable;

Total number of combinational cells: 16
Total number of sequential cells: 2
Total number of tristate cells: 0
Total number of level shifter cells: 2
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers:
Total number of usable buffers: 0
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters:
Total number of usable inverters: 0
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells:
Total number of identified usable delay cells: 0
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0

My .lib file does not have cell footprints, according to the Innovus user guide this should be fine as it figures out the footprint automatically, depending on functionality.
This is the output from 'reportFootPrint':

# footPrint: INVX1 nrCell: 3 Library: <hidden_bc>
Library:<hidden>
INVX1 INVX1 1 66.039 64.064
Y=(!X)
INVX2 INVX1 2 32.803 32.654
Y=(!X)
INVX4 INVX1 3 16.598 16.955
Y=(!X)
# footPrint: INVX1 nrCell: 3 Library: <hidden_wc>
Library:<hidden>
INVX1 INVX1 1 130.344 127.401
Y=(!X)
INVX2 INVX1 2 64.316 65.580
Y=(!X)
INVX4 INVX1 3 32.618 34.204
Y=(!X)

Clearly, Innovus also sees that indeed it is an inverter and detects all inverters having the same footprint.
Finally, I checked the 'dont_use' property, which is false.

Hence the question, how can I further debug this, or even better, what would be the solution?
(I am not allowed to upload the .lib files)

Thanks.