Dear All,
I want to synthesis my Verilog code via cadence but whenever I type rc comment at terminal It shows below error:
Checking out license 'RTL_Compiler_Ultra'... (0 seconds elapsed)
License 'RTL_Compiler_Ultra' checkout failed.
Checking out license 'RTL_Compiler_Physical'... (0 seconds elapsed)
License 'RTL_Compiler_Physical' checkout failed.
Checking out license 'RTL_Compiler_Verification'... (0 seconds elapsed)
License 'RTL_Compiler_Verification' checkout failed.
Checking out license 'RTL_Compiler_L'... (0 seconds elapsed)
License 'RTL_Compiler_L' checkout failed.
Checking out license 'Virtuoso_Digital_Implem'... (0 seconds elapsed)
License 'Virtuoso_Digital_Implem' checkout failed.
Checking out license 'Virtuoso_Digital_Implem_XL'... (0 seconds elapsed)
License 'Virtuoso_Digital_Implem_XL' checkout failed.
Cannot obtain 'RTL_Compiler_Ultra' license.
Abnormal exit.
also at my university virtuoso works properly.
I would appreciate your assistance with this matter.