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Encounter RTL compiler
Dear All,I want to synthesis my Verilog code via cadence but whenever I type rc comment at terminal It shows below error:Checking out license 'RTL_Compiler_Ultra'... (0 seconds elapsed)License...
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Innovus instance groups with multiple regions
Hi all,I have a specific question regarding instance groups and their placement. What I want to achieve is to add multiple instances to a instance group and then allow these instances to be places,...
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Libscore with Joules
Hi, I am trying to plot multiple liberty files performance at the single plot (w.r.t different FOM, e.g., delay, leakage etc.) any tool that able to perform this? have tried to use Joules but so far...
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Question about get_metric and report_metric
Hi experts, In Innovus platform, I tried to use report_metric and get a huge list of metric items in it, however when I do get_metric only very few of them listed. Even I tried to use e.g....
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Please help me I'm getting really wired signal violation
title.These two nodes are exclusively and directly connected; on the same net; U100:3D takes U136:O as input. I ran out of words to describe it. The thing is, why does U100:3D read error???? and I...
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Re-characterizing a tap-less cell library (Cadence Liberate)
Hi All,I want to re-characterize the existing library to a lower supply voltage. I have been provided the extracted (with parasitics) netlist (.cir) of this tap-less cell library by the vendor. > So...
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Balance Clock Tree Skew and levels of two different Block implementation in...
Hello everyone, I have two blocks separately implemented using the Encounter.They have huge CTS Global skew and i am unable to balance the CTS of two blocks and having hold violations between the very...
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Script for adding extra wires in Encounter
I added wires between certain fixed placed instances in my SoC encounter Layout manually from the gui by (Add wire "force special" ). These wires are close to each other by minimum drc separation to...
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Connectivity Violations in Soc Encounter implementation
I have implemented my layout in SoC Encounter and when I verify Connectivity, I have 7 violations (antenna violations). I routed certain wires manually in the implementation and mainly these nets have...
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How to fix certain Routing?
In my place&route implementation in SoC Encounter, I'm placing certain instances and fix their positions by the command placeInstance -fixed , then I route between them manually by long close...
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createMarker
Hi,I'm trying to create a mark based on dbGet .box property, but seem that it doesn't work. Below the code: set InstBBOX [dbGet [dbGet -p top.insts.name $FaninInstName].box] set lx [lindex [lindex...
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Multimode timing with create_mode and read_sdc, docs conflicting
I want to do timing analysis on two functional modes I have in my design.I'm using GENUS162.Searching around I've been told to do it this way:create_mode -name {MODEA MODEB}set CURRENT_MODE...
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No Simulation(vectors) generated in Stimulus generation summary during...
I'm using MMSIM121/111 and ETS131 and I am trying to characterize a cell where simulation vectors are not generated. It identifies all instances from subckt files using the model files:Following is my...
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INNOVUS 17.15 optDesign -postCTS -hold "9785 net(s): Could not be fixed...
Hi all,after run optDesign -postCTS -hold I found a lot of buffering nets failure with reasons: "nets Could not be fixed because of no legal loc."Do you have an idea on how identify that nets and to...
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filter_collection doesn't work whi variable
Hi all,I'm trying to filter a collection with a value.# following works, it report the same collection of ports_in but i_pippppset filt_ports_in [filter_collection $ports_in {hierarchical_name !~...
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Innovus: getting area value of a sub module from the hierarchy
Hello,I am trying to get the area value of a submodule from innovus through a script (after importing my design).My top_module is named grid_clb and the sub module of interest is "grid_clb_0_/fle_0_".I...
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Encounter Test: switch from command line mode to GUI
Hi,After building test mode in command line, I would like to analyze the inactive logic in ET tools GUI.How to switch from command line mode to GUI from with in the same tcl script?Regards,Venkat
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Reasons for remaining drv violations: Could not be fixed because there is no...
After a optDesign -postcts, the tool reports:Reasons for remaining drv violations:Could not be fixed because there is no usable buffer or delay cell for buffering.I'm sure that library have buffer...
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Systemverilog interfaces over hierarchical boundaries
I have experienced some back-end issues using systemverilog interfaces when and interface is traversing over hierarchical boundaries. I've tried to sketch the situation in the attached drawing.The top...
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what's "enable_domain_name_check" for Genus
Hi, I'm going through the Virtuoso Digital Implementation RAK. In the run file for Genus, there is one line setting an attribute:"set_attribute enable_domain_name_check 0 /".I don't know what the...
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