Extract logic cells from design to match cells provided by pdk?

Hello,

I'm completely new to this so please bear with me.

If I'm provided with some standard cells, and would like to use a design that I have in an FPGA to port to an ASIC using the provided cells, how do I determine which of the provided cells I will need? Is there a way to get from the RTL or FPGA design the logic cells that I can use in an ASIC? The library I have with the standard cells has multiple logic cells for the same function (multiple nands, nors, etc.), so how would I know which ones my design will translate into?

Thanks!