CTS DRV OPT Issue

Hi Folks,

I'm Seeing below issue in my design . I do have mutiple power domains in my designs.

Fixing clock tree overload: ...20% ...40% ...60% ..**WARN: (IMPCCOPT-2348): Unfixable transition violation found at snps_clk_UPF_ISO {Ccopt::ClockTree::ClockLogic at 0x2b8633f7a860, uid:A4648b7, a gt04p00 at (2038.028,767.448) in powerdomain MMCX in usermodule module cp_wrapper in clock tree SCAN_CLK} driving net o_rsc_epcb_tx_clk. CCOpt is unable to add buffers due to a dont_touch constraint on a verilog module or module port.

**WARN: (IMPCCOPT-2342): Unfixable transition violation found at CLK<2> driving net CTS_2. CCOpt is unable to appropriately place buffers to fix this violation.

.**WARN: (IMPCCOPT-2342): Unfixable transition violation found at cpp_wrapper/placeFE_OFC38604_clk {Ccopt::ClockTree::ClockDriver at 0x2b859d01ffb8, uid:A46357b, a CTSG g_aoinvp5f06p00 at (948.686,626.832) in powerdomain XYZ/INT in usermodule module XYZ in clock tree SCAN_CLK} driving net CTS_259. CCOpt is unable to appropriately place buffers to fix this violation.

what could be the issue here , can any one elaborate  & how do i fix this violation.

Thanks.