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trouble with auto routing minimum spanning tree, Layout XL
Hello,I'm having trouble with virtuoso 6.1.7 layout XL auto-routing.To show you my problem i created a hierarchical design consisting of two inverters in the first hierarchy, and a third inverter in...
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What is the command for opening the Xcelium Simulator ?
Hi All,I have compiled and simulated my system verilog file using the command " xrun -64bit -sv ./up_counter.sv " I need to observe the simulations in GUI. what are the commands to open the simualator...
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Wreal Assign in for loop not working
Hi,I have the below statements when given outside the forloop it works but within the forloop it does notgenvar i;real b;wreal a;generate for (i=0; i<20; i=i+1) begin assign a = b; endendgenerate
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Site Definition for Multi Height WB IO's
Hi,I have to design LEF files for my IO's which are developed in our organization, My question is that we are having all WB IO's of different sizes(both X and Y), do I need to define different site...
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Add Power Ring above Core. Innovus
Hi,I'm working on an ASIC that cointains pixels where each pixel has half area for Analog part and half Area for Digital part.I would like to know if for the digital part is possible to create the...
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Regarding to LUP.6 Error in DRC for digital circuit P&R
Hello everyone Could you please help me to find out why this DRC.LUP.6 error appears in my layout design. ( kindly see the photo)I am designing Read out circuit . RTL code implemented in verilog using...
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purpose of preCTS stage & latency/skew setting
Hi,I have a question about the purpose of the preCTS stage. preCTS stage is for drv fixing (max cap/tran/fanout..), also for HFNs optimizations.But why it’s needed to specify estimated clock latency...
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CTS DRV OPT Issue
Hi Folks,I'm Seeing below issue in my design . I do have mutiple power domains in my designs.Fixing clock tree overload: ...20% ...40% ...60% ..**WARN: (IMPCCOPT-2348): Unfixable transition violation...
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generateCapTbl command fails in INNOVUS because "Poly layer is not defined in...
I am running the following command in INNOVUS:generateCapTbl -ict <ict file> -output <captable file>to convert a .ict file to a captable file. I am getting the warning: "IMPEXT-6014 error...
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Content is the cornerstone of any digital strategy
First of all, it's important to understand that content marketing can serve as a complementary strategy to any other digital strategy. Its virtues are numerous since it helps your SEO on the web by...
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Hire the pro for some professionalism
The company website is the perfect domain to start with your business but when it comes to the profile building part, the "About Us" section may fall short of answers. What if there was something a lot...
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Cannot apply preserve attribute in VHDL source file
Hello,we are currently synthesizing a design that contains some triple modular redundancy and we want to keep Genus from throwing out whats redundant. So we tried to set the "preserve" attribute in our...
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**WARN: (IMPESI-429): No RC available on net xxx in INNOVUS 19.13
Hi,during optDesign postRoute log show a lot of warning IMPESI-429, what could be the reasons?
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Which variables give us the H/W information of the Core?
Hi,I am trying to develop a TCL script to automate the process of layout generation on Innovus.In order to do precise placements of pin in the script, I need some variables to get the information about...
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How to pass a string variable in the addRings command?
Hi,I am trying to pass my metal layer information for the addRing command using some string variables. However, the console prints an error saying variable not found.I am using the following...
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Joules: rtlstim2gate-Flow
Hello together,I'm wondering about the "-keep_libraries"-option of "rtlstim2gate" and why the dafault is to delete the Lib-information from elab-DB.In following example I use rtlstim2gate WITHOUT...
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Path exceptions modeling for ETM
On page 3 of Hierarchical Timing Analysis: Pros, Cons,and a New Approach , how is set_output_delay related to set_multicycle_path here in this case ?and how to re-code the path exceptions ? Any...
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The expertise of a pro
A Wiki page is easy to create, so it may seem. Give it a try and you will know that's not true. Academic writing is one of the most challenging forms of writing and with all the research it takes, it...
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Obtaining power traces using Cadence Virtuoso
Hi, all !!I am a beginner with the Cadence tools. I have an algorithm, AES-128, written in Verilog. I wish to obtain the current traces of the AES circuit using Cadence Virtuoso. Can someone kindly...
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Power planning of har dmacros.
I Have a SOC design with switcheble domains (AON, PDSWC for CPU, PDSWM for MAC) and a hard macro RF transceiver (TRX using PDSWM power net for digital, PDSWA for radio with dedicated power port). The...
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