For now we develop new project with number external hard macro devices (let's say it'll be few SPI modules, for simplification). Any of this external macro driven by generated clock in pretty similar frequency as main project. But main issue - we have analog-on-top flow and main digital pars is instantiated just as one of block in layout level.
I'm wandering is there some convenient method to manage timings/constraints for external macro (maybe some virtual macro connection). Basically we know exact timing relation for macros inputs/outputs and create it as library cell (with verilog, liberty and LEF) but obviously we cannot insert it to digital as it is not part of main digital part. Second problem - this macros will be moved and connection to them will be changed in different stages of layout so all the time we should need to recalculate input/output delay (with including numbers specified in liberty for macro).
In case there is exist some way to place this macro outside the boundary in innovus and count library numbers with some minor tuning of input/output delay - it would be great (without transfer this macros to layout).