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Problem with adding block rings
I am making a chip with a single-sided padring (ie not a ring as pads are only on the bottom). I created the floorplan in Innovus, placed macros and added a core ring without any issues. However, when...
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External Macro Placement and Constraining
For now we develop new project with number external hard macro devices (let's say it'll be few SPI modules, for simplification). Any of this external macro driven by generated clock in pretty similar...
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Library characterization using Cadence
Hi,I am trying to build a customized standard cell library using cadence. Right now, I met the problem to run the automatic library characterization. I searched online find there is an ELC tools....
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Query nets/cells causing DRVs using Tcl or dbGet commands to automate ECO flows
Dear all,I'm currently facing some issues with signoff timing closure for a highly congested block design.In short, the flow runs fine up to signoffTimeDesign in Innovus, however I'm not able to find...
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coonverting binary to decimal outout
Hı, I have 3 bit analog bits. I want to convert it to sıgned decimal output except 3'b100. because I want to get 3'b100 as a 0100(convert '-4' to '4'). Can u help me verilogA code for converting, please?
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Innovus connecting levelshifter power pin
Hi All,I'm new to BE design and I'm now at the stage to place&route. I have levelshifters in my design with a VDD and VDDL pin. The VDD pin is shared with all other STD_CELLs so is connected by...
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Should Run Post Route Again after DRC fix?
Hi,after i run post-route in innovus, i want to verify my design using commands check_drc, delete_routes -regular_wire_with_drc, route_design. Then should i run again post route timing analysis and...
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Power Analysis via Innovus
I faced two issues when I ran power analysis through Innovus.Firstly, according to"Basic" tab in "Run Power Analysis" window, the unit of Dominant Frequency is MHz, while it shows GHz during...
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[INNOVUS] failed to save holdtimer due to IO error (IMPOPT-7118)
Hi all,I got this error message (IMPOPT-7118) during hold fixing in optDesign -postCTS -setup -hold, then INNOVUS crash by internal ABORT signal. Can you help to solve this issue.ThanksHuy
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INNOVUS Placement regular structures
HelloMy current project have wide area and pretty big part of it are regular structures (like registers and some comb schematic) which duplicates about 512 times.Which of way are more relevant and...
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[INNOVUS] Cannot import timing library files. IMPSYC-2
Greetings,I have recently begun using Innovus to implement a digital circuit. I have a simple verilog design of a majority voter, and my goal is to walk each step the digital implementation process....
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IMPESI-3490 Error in Tempus
Hi,During ECO generation in Tempus I'm getting the following error on which Tempus exits. What is SMSC w.r.t below & how to set this?**ERROR: (IMPESI-3490): cdB based analysis is not supported with...
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Innovus write_netlist -phys with no POWER/GROUND INOUT in main module
Hello all,I am using Innovus for my physical synthesis.I am writing the netlist with the command: write_netlist -phys ../results/logic_control.vMy power/ground nets are DIGI_VDD and DIGI_GND. However,...
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[Voltus] Why static IR drop require timing window (TWF) file?
Hello all, I got 2 questions about Voltus static power analysis.1. Can you help to clarify below concept in Voltus UG:It quite strange because switching power belong to dynamic power. 2. Why static IR...
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[GENUS] Different synthesis results using 19.11 or 19.14
Hi all!!I am using genus to synthesize a digital design using the globalfoundries FDSOI 22 nm tech. I have updated the tool version from 19.11 to 19.14 and, using the same the script for the synthesis,...
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voltus option power_enable_state_propagation?
Could I some information on voltus option power_enable_state_propagation? UserGuide has no meaningful definition of what this does exactly.Thanks,Kurt
View ArticleInnovus short ports with cds_thru block causing LVS error
Hello, I am trying to do PnR with Innovus and I faced an issue with the output layout where two output ports logic were reduced into being the same port, so Innovus decided to short them together by a...
View ArticleHow to route the 5th terminal of soi DeCap in innovus?
Hi! Our soi technology cells have the 5th terminal VBGP/VBGN, which means it should be connected for all VBGP and VBGN in innovus. However, the 5th terminal for DeCap would be ignored while routing...
View ArticleHow to vary βn/βp ratio for a cmos inverter?
Hi,I have built a cmos inverter (pmos2v and nmos2v) using cadence virtuoso. I need to vary the βn/βp ratio and plot VTC for the same. can somebody tell me from where do i modify this factor. i am new...
View ArticleFrozen Innovus GUI while executing Tcl script to highlight and zoom to wires
Hello,I am trying to execute the following tcl script:proc pause {{message "Hit Enter to continue ==> "}} { puts -nonewline $message flush stdout gets stdin}set rh_rpt_dir {...}set layers_names...
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