Greetings,
I have recently begun using Innovus to implement a digital circuit. I have a simple verilog design of a majority voter, and my goal is to walk each step the digital implementation process. The digital library I'm using is UMC 65nm. I successfully generated a synthesized design through Genus. Now I am trying to import the design in innovus, but I have encountered issues. Both the verilog netlist obtained from genus and the lef files provided by the foundry are imported without problems. However, when I try to import the timing library through the MMMC view file the following warning comes up:
IMPSYC-2: Timing information is not defined for cell MAO222M1RA; Check the timing library (.lib) file and make sure the timing information exists for the cell and you can run the checkTimingLibrary command to verify if the timing library has complete information after the design is loaded. Type 'man IMPSYC-2' for more detail.
And the following error:
IMPSYT-7007: clink executable was not found.
The cell MAO222M1RA is a logic gate, and when I checked the timing library file it was there with all the appropiate delay information. I also tried using another library file with the ccs format and it didn't work either, as well as diferent verilog designs. The view file is very simple:
# Version:1.0 MMMC View Definition File
# Do Not Remove Above Line
create_library_set -name *name of the library* -timing {*file*}
I do not understand this issue since to me the library is well defined, and I don't understand what "clink executable was not found" means either. I was wondering if anyone could help me out, since I need the circuit delay but have been stuck here for some time.
Thanks.