Proper Timing Analysis using Innovus (and Genus)

Dear all, 

I need some guidance on how to perform a proper timing analysis in Innovus to ensure all paths meet the performance requirements. 

First, in my Innovus scripts, I feed the design (.v file) and the constraints (.sdc file) which both are generated from Genus. I also use the .lib files of the STD cells to create an MMMC file and read it before initiating the design.

Then I run the following commands to perform timing analysis at different stages of the flow:

set_ccopt_property target_max_trans 0.294
set_ccopt_property target_skew 1

setCTSMode -engine ccopt

create_ccopt_clock_tree -name clk -source clk
ccopt_design

## report clock trees and skew groups
report_ccopt_clock_trees -file reports/$module/clock_trees.rpt
report_ccopt_skew_groups -file reports/$module/skew_groups.rpt

## report timing after CTS
report_timing -unconstrained -delay_limit 1 > reports/$module/timing_report_postCCopt.prt

However, when I check the Hold time (for example), the tool show (N/A) next to the timing value. I'm assuming that there is something wrong I'm doing.

Also, I'm not sure how to tell the tool that the 'clk' signal is a clock - not a normal input. How should I be defining the clock signal? Is it only through the .sdc file as it is currently done? Once I define the clock properly, will the tool automatically insert clock repeaters (or clock splitters) to meet timing requirements and prevent issues like clock skewing? 

Many thanks

Anas

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The MMMC file: 

set lib /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcb018gbwp7t_270a

create_library_set -name fast\
-timing\
[list $lib/tcb018gbwp7tbc.lib]

create_library_set -name slow\
-timing\
[list $lib/tcb018gbwp7twc.lib]

create_constraint_mode -name my_constraint_mode\
-sdc_files /home/mchiama6/spiketrum/chip_m.sdc

create_rc_corner -name my_rc_corner\
-preRoute_res 1\
-postRoute_res 1\
-preRoute_cap 1\
-postRoute_cap 1\
-postRoute_xcap 1\
-preRoute_clkres 0\
-preRoute_clkcap 0\
-T 25\
-cap_table /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tcb018gbwp7t_270a/techfiles/captable/t018lo_1p5m_typical.captable\
-qx_tech_file /home/chip/qrcTechFile

create_delay_corner -name my_delay_corner_slow \
-library_set {slow} \
-rc_corner my_rc_corner

create_delay_corner -name my_delay_corner_fast \
-library_set {fast} \
-rc_corner my_rc_corner

create_analysis_view -name my_analysis_view_setup \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_fast

create_analysis_view -name my_analysis_view_hold \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_slow

set_analysis_view \
-setup {my_analysis_view_setup} \
-hold {my_analysis_view_hold}

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The .sdc file (Main commands):

# ####################################################################

# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Sat Mar 25 17:42:40 GMT 2023

# ####################################################################

set sdc_version 2.0

set_units -capacitance 1000fF
set_units -time 1000ps

current_design chip

create_clock -name "clk" -period 0.005 -waveform {0.0 0.0025}
group_path -weight 1.000000 -name C2C -from [list \
[get_cells {Subtractor/sig3_reg[5]}]

group_path -weight 1.000000 -name C2O -from [list \
[get_cells {Subtractor/sig3_reg[5]}] \
[get_cells {spike_generator_temp3_reg[2]}] ] -to [list \
[get_ports Con_Valid] \
[get_ports {Con_out[12]}] \
[get_ports {Con_out[11]}] \

group_path -weight 1.000000 -name I2C -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_cells RC_CG_DECLONE_HIER_INST/RC_CGIC_INST] ]

group_path -weight 1.000000 -name I2O -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_pins RC_CG_DECLONE_HIER_INST/enable] \
[get_pins RC_CG_DECLONE_HIER_INST/RC_CGIC_INST/E] ]
set_clock_gating_check -setup 0.0
set_clock_latency -max 0.005 [get_ports clk]
set_clock_latency -source -max 0.001 [get_ports clk]

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