How to create a wide route with coaxial shielding in Innovus?
Dear communityI have a design containing two IP blocks which are connected with "critical high-voltage" nets. According to the datasheet, these nets need to be routed with a trace that is at least as...
View ArticleWhich steps are necessary such that Innovus recognizes the link between I/O...
Dear CommunityI am working on a digital design where the I/O pads are placed in a predefined location. The floorplan is described in a .def file where the pads are defined as follows:COMPONENTS 55 ;...
View ArticleGetting error message in Innovus.
Whenever I am restoring my design, I am getting an error message "ERROR: (IMPTR-2101):Layer M10: Pitch=11520x9 is still less than min width=32000 + min spacing=640".The maximum defined metal layer in...
View ArticleWhy use "addstripe" command run so long?
I try to use "addstripe" command to add power net on ALPA,but its run so long(>24h),the detial as follows:%setAddStripeMode -ignore_DRC true -respect_routes all -skip_via_on_pin {Pad Block Cover...
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To delete the dangling wires
Like the picture below, there are a lot of dangling wires related to the VSS and VSS. I am wondering whether there is a way to delete these wires nad solve these warnings. Thank you very much!
View ArticleTo improve PPA on the layout
Dear all,I currently have the layout now, and I am wondering whether there are some commands or steps that can help me futher improve the PPA of the layout (Especially the power and slack).Thank you...
View ArticleInnovus/Encounter: Power pins are not connected to power rings
Dear all, In my RTL design, I have VDD and VSS as inout ports to supply the core design with power (not sure if this is how ideally is done?). However, when I do the placement and routing of the...
View ArticleInnovus: Assigning nets to pins
Dear all,I am seeking advice on how to efficiently assign different nets in my design to available pads so that they can be automatically routed using Innovus.Presently, I am utilizing pins by placing...
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Innovus: DRC Error - Special Wire of Net *** & Blockage of Cell ***
Dear all, I'm using Innovus to place and route an RTL design synthesised by Genus.After completing the routing, verify_drc tool highlights DRC errors on metal2 described as the following:Special Wire...
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Innovus: Routing Quires & General Advice
Dear all, I'm working on Innovus to place and route a digital design generated by Genus. When I look at the auto-routed layout, there are some points at which I think the tool should be able to do a...
View ArticleProper Timing Analysis using Innovus (and Genus)
Dear all, I need some guidance on how to perform a proper timing analysis in Innovus to ensure all paths meet the performance requirements. First, in my Innovus scripts, I feed the design (.v file) and...
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Innovus does not route net with non-default rule correctly
Dear CommunityI use the following code in Innovus 21.10 to route a net called "VSE2" that is supposed to be much much wider than the remaining netsadd_via_definition -via_rule via1Array -row_col {3 3}...
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xt-ld.exe cannot find CMSIS DSP library
Platform: iMXRT500SDK: SDK_2_11_1_EVK-MIMXRT595Xtensa Xplorer IDE version: 8.0.15 WindowsI am trying to link SDK_2_11_1_EVK-MIMXRT595\CMSIS\DSP\Lib\GCC\libarm_ARMv8MMLldfsp_math.a to a DSP application....
View ArticleInnovus: Placement of Bond Pads
Dear all, I'm trying to place bond pads into my design by following this solution.What I did is the following: 1- I have added the following at the top of my IO pad LEF file:PROPERTYDEFINITIONS PIN...
View ArticleIssues with generated .spef file using Cadence Innovus
I have generated synthesized netlist of my verilog design on Synopsys Design Compiler tool. For post layout results, Cadence Innovus tool was used and .spef file was generated. When this .spef file is...
View ArticleHow to constrain a large number of clocks and child clocks as asynchronous to...
Dear communityOur design has three main clocks. Let's call them clk1, clk2, and clk3. Each clock has several child clocks running at the same frequency. So the SDC file could look like...
View ArticleHOLD VIOLATIONS AFTER SIGN OFF STAGE
Hello All,I am doing digital synthesis for a type 2 digital Cdr at 500MHz in the 65nm gp process. At the end of postroute I don't get any setup or hold violations in my design.But after timeDesign...
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How to constrain a shared input pin that is either a gated clock or a signal
Dear communityPlease consider the following design:The design has two operational modes, and depending on which mode it is, the input port sclk serves a different purpose. Let us call those modes Mode...
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VERIFY GEOMETRY COMMAND IN INNOVUS
Hi All,I get four violations in wiring (shorts) in the sign off stage of pnr. When I run the drc on the generated layout it comes out to be clean.I have a few queries:1. How do I check which nets are...
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Innovus: Special Route doesn't connect PG rails to PG Rings
Dear all, When I use the sRoute command to connect the PG rails, sRoute dosn't connect the rails to the PG ring, instead it stops routing at the core boundary, as shown below:Is there a way to fix this...
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