How to constrain a shared input pin that is either a gated clock or a signal

Dear community

Please consider the following design:

The design has two operational modes, and depending on which mode it is, the input port sclk serves a different purpose. Let us call those modes Mode A and Mode B.

• In mode A, the input sclk serves as a clock input. Here, the output if_sclk of the module i0_ctrl is active. if_sclk is a gated clock running at the same frequency as sclk, i.e. the tool (Innovus 21.10 in my case) is supposed to create a clock tree on this net.
• In mode B, the input sclk serves as a normal data input. Here, the output test_data of the module i0_ctrl is active. This signal is used by some logic that is synchronized to the internal main clock clk.

The two outputs of the module i0_ctrl are exclusive, i.e. only one of them can be active at any time. Which operational mode is used is controlled by external signals (not relevant for this question). The two clock domains sclk and clk are asynchronous. The pad has a serial resistor and some protection components. That's why the internal net (sclk_in) has a different name.

Here is how I would write a minimal SDC file:

SDC File for Mode A

create_clock -name "clk" -period 62.5 -waveform {0.0 31.25} [get_ports clk]
create_clock -name "sclk" -period 250.0 -waveform {0.0 125.0} [get_pins i0_pad/Y]
create_generated_clock -name "if_sclk" -divide_by 1 -source [get_pins i0_pad/Y] [get_pins i0_ctrl/if_sclk]
set_clock_groups -asynchronous -group {clk} -group {sclk if_sclk}

SDC File for Mode B

create_clock -name "clk" -period 62.5 -waveform {0.0 31.25} [get_ports clk]
set_input_delay -clock [get_clocks clk] -add_delay 20.0 [get_ports sclk]

Whether this is correct or not I do not know; I was unable to find a simiar example in manuals. Here are some questions that came up:

1. How to correctly define gated clocks? Is the approach with create_generated_clock correct?
2. To what object should the clock sclk be assigned in Mode A? The port? The input or output pin of the pad? The pin of the module i0_ctrl?
3. How do I constrain the port if_sclk in Mode B? This net technically still is a clock net in Mode B; it just does not have a driver that generates an actual clock, i.e. all connected logic is inactive. Can I just leave this black or do I need to specify it as a clock anyway? I tried both variants. Boch can be imported into Innovus without generating errors, but the resulting clock tree is different and I do not know which one is correct.

Thank you very much for any suggestions.