Doing synthesis with a composed cell in netlist [GENUS][Verilog]
Hi.I want to synthesize a digital block prioritizing a custom Verilog netlist made of standard cells. I have created the following module as AOI.v file:moduleAOI(a, b, c, d, y);input a,b,c,d;output...
View ArticleQuestions about a constraint in the SDC
I encounter the following command while reading the SDC:create_generate_clock [list [get_pins pciex4_2_clk] [get_pins pciex4_2_clk_clks]] -name pciex4_2 -source [get_port xx ] -dvide_by 1Now I know...
View ArticleCannot load in netlists in Innovus: syntax error？
Hi, when I try to load in design to Innovus, it returns error message:Reading netlist ...Backslashed names will retain backslash and a trailing blank character.**ERROR: (IMPVL-209): In Verilog file...
View ArticleTop-Level PnR in Innovus: Routing Power to Blocks
Hi everyone, In our design we will be performing a top-level PnR in Innovus, where we will be routing between blocks (macros) as well as routing the pads to the blocks. I was wondering if there was any...
View ArticleInnovus Error in Multi-thread Placement
I'm using Innovus 18.10 and there is some error with placement and I could not find out why. The server CPU has 112 cores. Innovus used 64 threads, which was set by "set_multi_cpu_usage -local_cpu 64"....
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Genus standard cells to module
Hi, I have a TCL script for synthesizing a full adder (see below).I am trying to modify the script so that when Genus opens, the schematic represents the circuit in module form.I don't want to see the...
View ArticleVoltus Rail Analysis Fail: No Current Source
I wanted to do an IR drop analysis and followed the procedure provided in the Cadence tutorial video: power analysis, specify power net, power pad location file, run rail analysis.It did not run...
View ArticleSegmentation Fault (core dumped) when invoking INNOVUS211
Dear all, I am trying to run Innovus (v21.11 64bit) on Red Hat 7.9 Linux, the tool tries to run but ultimately a "segmentation fault (core dumped)" message appears. I get the same issue when trying to...
View ArticleecoDesign - Failed to find design data with specified top cell name
I have a folder named "seed.enc.dat" file, and my gate level netlist is called "design.v", and its top module is called "SEED_key_sched".But after I use "ecoDesign ./db/seed.enc.dat SEED_key_sched...
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DRC Violation
I got 5 DRC violations after routing in innovus version 21.13, is there any solution that can solve all these DRC Violations?Thanks!
View ArticleAnnotating multiple dmmmc sdf files with Xcelium
Hi all,After running STA multi-mode-multi-corners I get more than 20 sdf files. I would like to somehow check all of them without running manually more than 20 times xcelium.Is there any way of doing...
View ArticleGetting Started
I am just getting started in digital design flow and in the process of bringing up a tsmc digital PDK. I am using genus and innovus v16.10 for synthesis and pnr. I have an understanding of the files...
View ArticleDigital qrcTechFile vs RF qrcTechFile?
Is there a difference between the digital qrcTechFile and the RF qrcTechFile?Thanks Gabriel
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DRC Violations on Auto-generated layout using Innovus
Dear all, I have a design that is synthesized by Genus and I'm trying to auto-generate the layout using Innovus. Although the layout is auto-generated, the layout shows DRC violations. All violations...
View ArticleFailed to open Modus
Hi,When I run modus i face the following message:Checking out license: Genus_Synthesis (13 seconds elapsed).License 'Genus_Synthesis' (main version: 20.1, alternate version: 20.1) checkout...
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How to force sroute of Innovus to go to the highest layer before routing...
Dear communityI am using Innovus version 21.10 to implement a digital design in a 180nm process with 6 metal layers.Layer 1,3,5 are horizontal routing layers, and layer 2,4,6 are vertical routing...
View ArticleExport layout from Innovus to Virtuoso
Dear all, I have a design on Innovus and I would like to take it to Virtuoso for verification.What I found so far is that there are two ways to do it:using GDSII + DEF filesusing OA cell view.Method 2...
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GDS DBU and Database DBU mismatch
Dear all, I'm trying to import a layout from Innovus to Virtuoso as a GDS file. When I export the GDS file from Innovus, the following is shown: This clearly states that DBU is set to 2000 in the...
View ArticleHow to set the units for an SDC file in Innovus (**WARN: (TCLCMD-1461):...
Dear communityThe SDC file I am using in my digital design has the two linesset_units -capacitance 1000fFset_units -time 1000psReading this file into Innovus 21.10 leads to an "(TCLCMD-1461): Skipped...
View Articlewhat's the "FTerm" mean(IMPSYC-1265)?
The commands I have used are as follows:%addNet -power AVSS%dbGet top.nets.name AVSS AVSS%assignPGbumps -nets AVSS -selectedWARN(IMPSYC-1265): FTerm was not found for net "AVSS" ,AVSS has been...
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