Hi, I have a verilog netlist as follows
module XYZ
(
input a,
input b,
output [12:0] y
) ;
OR2_X1M_A12TH_C35 g67 [12:0] ( .A(a), .B(b), .Y(y) ) ;
endmodule
when i import it using import design form in encounter v12 following error occurs
**ERROR: (ENCVL-209): In file '../Desktop/acc_macro/buss_check.v', line 9, syntax error at :.
Verilog file '../Desktop/acc_macro/buss_check.v' has errors!
any suggestions?
-Arslan