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how max_sink_trans value is going to affect the timing of my design
 Max_Sink_trans value specifies the clock slew, can some one please let me understand how it is going to affect the timing of my design? Please let me know if it has to be less than the...
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Script to automate synthesis
Hi, How can I automate synthesizing a behavioral model using SoC Encounter and also get its sdf outputt using some sort of scripting?
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Default Load in RTL Compiler
I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler..1 )When i estimate power my RTL compiler does produce a result but I am uncertain...
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Set default load in Library generation
I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler..1 )When i estimate power my RTL compiler uses a a load I am unaware of . Is is...
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More info on error/warning messages
Hi I'm to EDI. Where can I get more details on error or warning messages to fix them? Specifically, I got the errors:**ERROR: (ENCSPR-3):Â Special Route file version (0.-134531535) is not compatible...
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Placing certain group of instance
Hi everyone, Wondering if it is possible to place certain group of instance at the beginning of the PNR flow? Not a single of. BecauseI know that placeInst could be used for placing single instance....
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dbFTermType
 Hi All , while i am filtering the clock IO pins from all IO pins i am using dbFTermType <ftermptr> , but this command is giving the result as dbcNormalTern for clock IO pons also instead it has...
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Verilog in and spice out procedure?
Dear all, I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out. How does this process actually work? What the the...
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net_delay calculation
 Hi All , when i open attribute editor of a net i am seeing net capacitance and total resistance . How does tool calculate these net capacitance and total resistance?  Thanks in Advance. Â
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Soft blocks (modules) in Encounter
 Dear Friends,Can anybody explain why after loading verilog to Encounter I'm not able to see modules (each of them has std.cells in it) in the fllorplan mode?Modules exist in verilog and I'm able to...
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netlist import failed...
Hi, I have a verilog netlist as followsmodule XYZ (  input a,  input b,  output [12:0] y  ) ;  OR2_X1M_A12TH_C35 g67 [12:0] ( .A(a), .B(b), .Y(y) ) ; endmodule when i import it using import design...
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Power domains or not?
Hi all,I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins.But the actual voltage of all cores is 1.8V. For testing only one core...
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short violations
 HI All,In My Design I got short violations on signal nets only .In my case one net create huge violations and another case some drc violations are there .I did this way to rectify drc...
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dumping power pins and their connectivity
 Hi All,Iam working on place route for mixed signal design and i have a verilog netlist with PG pin connectivity defined for analog macros and for the digital cells , iam using global net command....
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relative placement with macros
Hi, I am trying to place a design with some macros and I use relative placement for these. Since the design is fairly large and only one (shared) 4 core machine is available I try not to use the GUI...
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how to use the floorplanning options in encounter efficiently
There are multiple options in encounter to floorplan. I'm confused how to use them efficiently. Below are the options I tried and I still couldn't converge on my setup times. My design has got more...
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Prevent OptDesign in between paths
I am trying to prevent Optimization between a path. set_dont_touch, works only for the complete net, but not between a begin pin to a End Pin.Is there any other option to achieve this type...
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single analysisType does not work with SIAware flag in ETS
Hello, I am trying to run ETS with the below setting and I get no paths founds in my report_timing. set_analysis_mode -analysisType single -cppr bothset_delay_cal_mode -engine aae -SIAware trueThe...
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problems with report_timing when using user defined path groups
Hello, I am using the following options in report_timing in ETS 12.0. set_global timing_report_group_based_mode truereport_timing -max_paths 50 -nworst 10 The documentation says it will print the WNS...
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Generating blockages on Active layer
Hey everybody, I'm working in a very young process that only has one metal layer available. Because of this, I'm having to use POLY to route as well. I am currently having issues with routing POLY...
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