Hi All,
I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.
=====================================================
--> <folderPath>/BackEnd/
* LEF P & R model (in <folderPath>/BackEnd/lef)
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.3.lef
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.lef
- foa0i_r33_t33_generic_io.3.lef
- foa0i_r33_t33_generic_io.lef
- header3_V55.lef
* physical compiler database (in <folderPath>/BackEnd/phycompiler)
- foa0i_r33_t33_generic_io.3.pdb
- foa0i_r33_t33_generic_io.3.plib
--> <folderPath>/TECH/
* Cadence DFII environment files (in <folderPath>/TECH/dfii)
- FOA0I_R33_44.tf
- cellout.tab
- display.drf
- layer.DEFINE
- pg_sout3.tab
- pg_sout4.tab
- streamOut.map
- streamin.tab
- txtfont.tab
====================================================
Which is better out of the two options
1. Do IO placement in virtuoso itself
2. Take it to encounter - (How to do it ?)
Thanks,Shameel