Hi all,
It is my first time on this forum so please may apologize my lack of knowledge in some matter.
I'll put my problem in context:
We are designing a mixed-signal project in technology tsmc65nm. I work on the digital side and I have problems to port my design in virtuoso. Right now, I have generate a digital circuit for my college in order to integrate it in his analog design in Virtuoso.
I succeed in creating the «gds» file and somehow importing it to Virtuoso but once I open it, the layer doesn't match and I have a bunch of DRC violations.
Then I create a library and I imported the «lef» file of my standard cell (which also include layer etc) and I attach it to the technology file corresponding (*.tf). Then I created a «.def» file and I import it to this new library. In this way, I was able to see the good layer but no layout view of the standard. I tried some trick to get them but with no success...
I saw that it would be possible to translate «lef» file to oa library and then the transfert between Encounter and Virtuoso is much easier. But I tried but I think that I'm mixed up with all the required file.
I can tell you the type of file that I have:
.lef => with the layer, standard cell etc
.map
.tf
If someone know a way I could solve my problem either by creating the OA lib of telling me the way to be able to transfert my design to Virtuoso and be able to see it with the standard cell layout and then pass the DRC, I would be more than happy.
If I misunderstanding some matter, feel free to educate me!
Thank for your support