LVS verification for gds file from Cadence SOC Encounter

 Hi,

How to verify the LVS for gds file from Cadence SE. I have used 65nm STM standard cells for generating netlist file for layout and schematic design.  i am getting mismatch erros in Calibre LVS report  (INCORRECT). How to avoid bulk pins (vdds, gnds) in schematic, and missing instance (nsvtlp, psvtlp) cmos065.

Thank you!!