Power Analysis EPS vs. EDI

Hi there,

we are using EPS to generate power reports for a gatelevel netlist produced by EDI. A comparing EDI power reports and EPS power shows big differences in the switching power (see below).

Where do these differences in the switching activity come from, since we are using the same netlist, and the same setup?

EPS report_power with test.vcd for switching acctivity (mW, %)

Total Internal Power:       18.06020172      73.3519%
Total Switching Power:       4.23011635    17.1807%
Total Leakage Power:         2.33098969       9.4674%
Total Power:                24.62130789

EDI report_power with test.vcd for switching acctivity (mW, %)

Total Internal Power:       18.41854781      66.1447%
Total Switching Power:       7.09351231    25.4742%
Total Leakage Power:         2.33379140       8.3811%
Total Power:                27.84585164

report_power script used within EDI and EPS: 

    reset_power_activity
    read_activity_file -reset
    set_analysis_view -setup v_setup -hold v_hold
    set_power_analysis_mode -analysis_view v_setup -method static
    set_dc_sources -power gnd -voltage 0.0
    set_dc_sources -power vdd -voltage 1.0
    read_activity_file $programlist.vcd -format VCD -reset -report_missing_nets true -scope coreva_cpu_system_tb/coreva_cpu_generic_bus_wrapper_1
    report_power -outfile powerReports/$programlist.pwr
 

Here is our setup for EPS (same as in EDI):

read_lib -min $::env(SOC_MIN_TIMELIB)
read_lib -max $::env(SOC_MAX_TIMELIB)
read_lib -lef $::env(SOC_LEF_FILE)
read_verilog coreva_cpu_generic_bus_wrapper.v
set_top_module coreva_cpu_generic_bus_wrapper
read_sdc $ENTITY._default_constraint_mode_.sdc

if { [ file exists "$ENTITY.sdf" ] } {
read_sdf $ENTITY.sdf
} elseif { [ file exists "$ENTITY.Setup.sdf" ] } {
read_sdf $ENTITY.Setup.sdf
}

setDesignMode -process $::env(SOC_PROCESS)

# MULTI MODE MULTI CORNER (MMMC) SETUP
create_constraint_mode -name m_hold -sdc_files"$ENTITY._default_constraint_mode_.sdc"

#RC corners
create_library_set -name best_library_set -timing"$::env(SOC_MIN_TIMELIB)"
create_library_set -name worst_library_set -timing"$::env(SOC_MAX_TIMELIB)"
    
create_rc_corner -name rc_worst -qx_tech_file"$::env(SOC_QRCFILE_BEST)"
create_rc_corner -name rc_best  -qx_tech_file"$::env(SOC_QRCFILE_WORST)"
 
# OCV derating
create_delay_corner -name dc_setup -library_set {worst_library_set} -rc_corner {rc_worst}
create_delay_corner -name dc_hold -library_set {best_library_set} -rc_corner {rc_best}
   
create_analysis_view -name v_hold -constraint_mode {m_hold} -delay_corner {dc_hold}
create_analysis_view -name v_setup -constraint_mode {m_hold} -delay_corner {dc_setup}
 
setAnalysisMode -analysisType bcwc

We hope some can give us a kick in the right direction.

 Best regards,

Marten