Clik here to view.
EPS TMPDIR environment variable
My log file shows: "environment variable TMPDIR is '/tmp/" When in the flow should I:' setenv TMPDIR /user/me/tmp '...to prevent EPS from using the /tmp/ directory on our machines.
View ArticleClik here to view.
How to Characterize the timing information for level shifter with two supplys?
HI, All Now, I want to characterize a level shifter cell with two supplys by ELC of ETS11.0, but I have no idea to setup the voltage for the two supplys respectively,I only know how to set the default...
View ArticleClik here to view.
ncvhdl compilation error
Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0;...
View ArticleClik here to view.
Minarea violation in SOC encounter
Hi, I want to know what "Minarea violation" is, and how can I solve it?? I have 3 Minarea violations in Geometry verifying by SOCencounter... thanks alot
View ArticleClik here to view.
Design partition in soc encounter 10.1
I am new to soc encounter, Can anyone guide me how to do the design partition flow. Due to lincese problem It does not read the Power domain (Low power) commands, MSMV and cpf file. The design TOP has...
View ArticleClik here to view.
Help with designing of NEMS switch in pspice
Hello all,I would like to design a three terminal NEMS device netlist which has the certain V-I characteristics, capacitance and switching speed . How do i do this .?Please help me, Any Leads would be...
View ArticleClik here to view.
IC5141 CDL in skipping passive devices
Hello everyone, I'm trying to import a CDL netlist that contains IO pads and logic into IC5141. The issue I am having is that it skips all of the passive devices within the cell. This particular cell...
View ArticleClik here to view.
Import Synthesized Verilog Netlist to Virtuoso
I am trying to import a synthesized verilog netlist to virtuoso (IC615). The problem I have is, the standard cells are missing. I do not know what library file I should add to the library manager, as...
View ArticleClik here to view.
script to run IRUN
Dear, I am trying to run (IRUN) script to generate a vcd file inside many folders so my script is like that :----------------------------------------------------- #!/bin/tcsh#created @aa835# script to...
View ArticleClik here to view.
ELC not using spectre
ELC seems to always read in files as spice format even though I have "simulator lang = spectre" without the quotes at the top of every .scs file. In addition I have:set_var EC_SIM_NAME...
View ArticleClik here to view.
Cadence ELC not recognising SPECTRE format
Halo, I am using ELC to characterise a new standard cell library. I am using a SPECTRE .scs model file, but it seems that ELC is not recognising this file format correctly, as it complains about...
View ArticleClik here to view.
ELC (Simulation failed with the status 25600)
Hi, I am trying out ELC and found one issue, db_spice couldn't pass, output looks like below: elc> db_spice -s spectre -p typical -keep_log -keep_wave DESIGN PROCESS #ID...
View ArticleClik here to view.
ELC cannot run db_spice
hello.I use ELC to character INV and NAND2,when I type db_spice ,it shows DESIGN PROCESS #ID STATUS...
View ArticleClik here to view.
Litho physical analyser is used to reduce variations in 90 nm and below. What...
Hi,I am currently creating a LPA flow from 28nm. I was reading the user guide of this tool. It primarily detects hotspots. What are these hotspots ? Please explain in detail or point me to any...
View ArticleClik here to view.
Parasitic Extraction including floating stripes on top metal layer
I am designing a digital block which has stripes on the top metal used to route signals over the block. I created them with the addstripes command. The stripes are connected to a floating output pin of...
View ArticleClik here to view.
Pads on 3D IC
Hello,I am a little confused about an issue. At the design of a 3D ic is it possible to have I/O pads at all the different layers? I have see many algorithms (i.e. for partition, placement) claiming...
View ArticleClik here to view.
Cannot find output terms for clock synthesis
Hi, I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that **ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO. Here pad inastant name is "clk_in"...
View ArticleClik here to view.
Power Analysis EPS vs. EDI
Hi there,we are using EPS to generate power reports for a gatelevel netlist produced by EDI. A comparing EDI power reports and EPS power shows big differences in the switching power (see below).Where...
View ArticleClik here to view.
EDI Placement Density Screens Honored after Optimization?
Dear All,Can anyone tell me if Density screens are honored after optimization? I'm trying to applyplacement density screens in EDI 14 but they are not honored after optimization.Thanks,Aram
View ArticleClik here to view.
hold fixing in scan chains
Hello, In the design I'm working on I have lot of small hold violations (~30ps) in the scan chains. The design is small, and the FFs in the scan chains are placed very close together. So the data path...
View Article