Hi guys,
Excuse me, I dont know that Im in the right place or not.
I need to build a simple digital logic for my Analog section. As I checked DRC it was OK. However in the case of LVS it seems that there is a problem with utilization of standard cells. For this reason I built a simple test bench to find the solution. But I couldn’t. During LVS I face with this error which says that there is no vdd and gnd in layout source. I don't want to edit the standard cell so is it possible to mitigate it without changing the cell. 
