PG ports in the original VHDL IP duplicated by VSS_0, VDD_0

Hello,

When running Encounter PnR on VHDL design, which includes declaration and hierarchical connections of the PG ports VSS and VDD, it creates an extra set of ports VSS_0 and VDD_0 in addition to original ones.

I understand that these VSS and VDD from the RTL considered as logical and not physical, but since it is an IP I cannot remove it.

What is proper way to avoid the creation of these VSS_0 and VDD_0, without modifying the RTL?

Thanks and regards,
Boris