Hi all,
I am working on the timing characterization of standard cells on an SOI process. The tool I am using is Cadence Encounter Library Characterizer (ELC) version v11.12-s002_1. However, the SPICE model of this technology defines transistor as a level=76. The characterization process always ended with errors, and it seems that the ELC cannot recognize the transistors.
So, is my ELC version not new enough to support level 76 models?
Thanks a lot in advance for any suggestions.
Tom