How to make CTS trace through a custom block ?

Hello,

I have a case where a clock (input_clk) enters my design and goes to some logic, but also goes to a custom block which has a non-overlap clock generator inside of it. The in-phase output of the non-overlap clock generator (phi1) then goes to more logic in the design. Since this signal is essentially a delayed version of the input_clk I believe the most accurate way to have CTS properly create the clock tree would be to simply model this custom block as a DLY or BUF cell so setup/hold time is properly checked (phi1 will clock ICG cells which are enabled by signals launched from input_clk and thus I don't think setting phi1 as another clock root is a good idea). 

I have made the lib/lef of my custom block exactly match the STDCELL lib/lef of a BUF/DLY cell in hopes that CTS would think of it as such and trace through, but that does not work.

If anyone has any idea on how to clue CTS to trace through a custom block that adds delay, I would be very interested. 

Thanks.