ccopt_design - ERROR ENCCCOPT-1135
Hello,I am getting the following error when running "ccopt_design -cts":ERROR ENCCCOPT-1135 - CTS found neither inverters nor buffers while balancing."AutoCTSRootPin * Buffer ..." doesn't really...
View Articleccopt - MacroModel
Hello,Is there a way to define MacroModel timing exception for CCOPT similar to the old fashion CTS:specifyClockTree -update { MacroModel pin top/core/special/special_reg/CLK 2.5ns 2.1ns 2.5ns 2.1ns...
View ArticleEDI 14.13 crashes with SEGV during placeDesign
Hi there,we are using Encounter v14.13-s036_1 (64bit) for P&R of our Designs. When running placeDesign on a big network on chip design, encounter always crashes during placement of the design (see...
View ArticleHelp FileStim
Hello!I want to use a text file create with NotePad tu use in a FileStim, but I Cant because all the time I have the next error: ERROR(ORPSIM-15332): Unable to open stimulus file 300khz.stm.Im using...
View ArticleglobalDetailRoute vs. routeDesign
Hello,What is the difference b/w these two command : globalDetailRoute and routeDesign?Thanks and regards,Boris
View ArticleWhich metal layer is estimated by synthesize_ccopt_flexible_htrees command?
Hi,I want to build a flexible htree and tried to run synthesize_ccopt_flexible_htrees command. It was build but lower level metal (thinner metal) is being used than expected so too many clock buffers...
View ArticleHow to make CTS trace through a custom block ?
Hello,I have a case where a clock (input_clk) enters my design and goes to some logic, but also goes to a custom block which has a non-overlap clock generator inside of it. The in-phase output of the...
View ArticleHow to avoid "leap frog" situation when generating a long shift register with...
I have a long shift register that is synthesized with RTL compiler using my customized standard cell. LEF and liberty file is also generated with virtuoso and liberate. (version is ic616 and liberate...
View Article[Voltus] set_pg_library_mode command option -power_pins?
Hi,im using voltus for power grid view generation, what does the "-power_pins" option inside the set_pg_library_mode command do exactly? for example,set_pg_library_mode \ -celltype macros \...
View ArticleEnabling SI aware CTS and Optimization
Hi All,I have timing violations because of cross talk in my design at post route stage. All the violations are purely because of cross talk. I want make sure that this is taken care from CTS, post...
View ArticleHow to calculate 'Hold' time in the endpoint report?
Hi,I want to know how to calculate 'Hold' time in the endpoint report to identify what is wrong. Could you give me the formula to calculate this? Is there any commands to list them up?Path 1: VIOLATED...
View ArticleIs there a way to add a normal buffer on a clock path
Hi All,I have scan timing path where clock path is connected to SI pin as data and I have a huge hold violation on it.Is there a way I can add a normal delay cell on the endpoint. ecoAddrepeater giving...
View ArticleRC Physical Flow - Spare Module
Hello,I am trying to convert the conventional RC-Encounter flow to RC-Physical.Since the placement is loaded through the DEF file generated by RC-Physical script, there is no more need to run...
View ArticleHow CCOPT determines the buffers needs to be used
Hi,I am using CCOPT for cts and I am not specifying any buffers list for CTS. If you dont give any input how CCOPT determines the buffers to be used? I am meeting skew and latency requirements.Is...
View ArticleHow to dump timeDesign reports with path based analysis ?
Hi Is there any way to dump reports with path based analysis?does time design reporting supports this?Regards,Anil
View ArticlePlacing Tie-Down Cells in EDI design
HelloI have a design in which I need to place Tie-Down cell repeatedly after certain number of cells to make the bulk ( analog substrate) contacts. My standard cells does not have analog ground ,...
View ArticleResolving MinStep Violation
Hi,I've completed place and route of a design that I'm working on. And during the DRC checks, I've received a few MinStep and MinArea violations. Attached in the photo below are the Minstep violations....
View ArticleFunction call in verilog
I have written a verilog for ma project work. In it,I wrote the followin code:for(i=n-2;i>=0;i=i-1)beginge (w[2*i+1],w[2*i],w[2*i+2],w[2*i+3],a[i],b[i]);endI am getting error. how should i declare '...
View ArticleStreaming out GDSII from Encounter (EDI) - gds doesn't include standard cells
HelloI am trying to stream out a GDS file from Encounter EDI, but I notice that the GDS file does not include the standard cells.I only have a library file and LEF and tech files. I don't have access...
View ArticlePlacement Density
Good morning everybody,I would like to ask a question about the placement desnity and the effective utilization of a digital block designed using standard cells.During the floorplan I set the core...
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