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layout of Digital controlled dc-dc converter
Hi,I have designed dc-dc converter with digital control. I used the ideal ADC block and rest blocks are according to design. i checked the simulation which is running smooth. Now I am doing layout of...
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Import DEF to Encounter
hi everyone,this is my current situation. I need to do pnr but the .lib files are not available. So I try import DEF file, which is export from Virtuoso, to Encounter but I've faced some problems like...
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Problem in implementing eco on EDI on a legacy database which used another...
Hi,I was trying to implement an eco on EDI. The catch is the database I am implementing it on is not created by edi. I have a full def of the design. And these are the steps that I did.Created a...
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characterizing pex netlist using elc
Hi,When I'm running ELC to characterize pex netlist of my cells, i'm facing the following problem. [WARNING(db_spice)]No spice simulation to do, please check the cell/process list for any errorBut when...
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Question about LEF files
Hi all,I'm going to implement a simple filter logic and I have two main questions in the following. First, When I use the RCP flow there are some warnings associated with the provided LEF files from...
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optDesign -postRoute in PAC flow
Hi,I want to optDesign in Post Assembly Closure Flow in soc Encounter. But it is a limited access feature. I get the following error when i attempt it. **ERROR: (ENCSE-24): 'optDesign -postRoute in PAC...
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SDF file has same delay value for min and max settings
Dear Sir, I am using the following tools/libraries.Tool : First EncounterVersion : v06.20-p006_1Standard Cell library: UMC0.13um Logic HS (FSG) process high density core cell LibraryThe following...
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generation of lef-tech map file
HiIs there any cadence Tool which generate the lef-tech map file using extraction tech file (.tch) anf technology lef file(.lef)
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how to caluclate switching power of a full adder in cadence spectre simulator?
Good afternoon everyone..please help me how to caluculate switching power of a full adder or any digital circuit in cadence? thank you
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timing window generation
Hi All,Is there any way in EDI to generate generalized timing window file in EDI.Anil
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Sign-off extraction in RC extraction set-up
Hi,I wnat the spef file from Rc Extraction setup when i set in default mode of RC extract setup and run the command "extractRC" the rcout gives the spef file.butwhen i set in sign-off extraction mode...
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Layout
Can anyone help me to explain that when we make layout and do DRC, multiple files are being created. For example; inv.dlist.0001 and so on.Are these important or we can delete it.
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How to use the physical IP when physical design flow?
Hello,I have a problem to use the physical IPs when performing physical design flow with Encounter.For packages with FE view, it includes these directories: astro cell_list doc lef primetime symbols...
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How to add an extra annotated capacitance on a net
Hi All,Is there any way we can add an annotated capacitance on a net.like in set_annotated_delay .. Is there any command to add capacitance to a net ??Regards,Anil
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Power Factor - Number of Cores - Encounter -Reg.
I am designing "Microprocessor without interlock Pipeline Stages (MIPS)" processor using Verilog HDL, RTL Compiler, Encounter.How can I calculate the power factor for the design using Cadence.How can I...
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Specifying multiple scopes in SDF command file
If there are multiple instances of the same module in the design, how do we define multiple scope in sdf command file.Eg: if we have a module instantiated as dut under hierarchies x1, x2,x3, ... so I...
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Top-level routing with NanoRoute fails in Encounter top-down hierarchical...
Dear all,I'm currently working on a full-chip design by adopting Encounter top-down hierarchical methodology with a master/clone flow on repeated instances defined as black-boxes. According to various...
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MergeLef
Tool: Encounter 14.2The design kit has 3 LEF files for the following.Header file (Metal & via information)Core cellsAntenna Information for metals & core cells.During place & route, I add...
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Soft error with Voltus?
Hello,I study how soft errors (modeled by a exponential current source connected from the drain to the bulk) propagates in a circuit using Virtuoso (Spectre).However, now I want to simulate a bigger...
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Clock mesh delay, SDF, and timing..
Hi,I am recently trying the EDI clock mesh flow and found very limited info from the manual. With AE's help, I finally can generate a clock mesh. However, I still have some questions regarding the...
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