Power Factor - Number of Cores - Encounter -Reg.

I am designing "Microprocessor without interlock Pipeline Stages (MIPS)" processor using Verilog HDL, RTL Compiler, Encounter.

1. How can I calculate the power factor for the design using Cadence.
2. How can I know number of cores in the design.

Help me to resolve these issues. Correct me if any mistakes in the post.