Hello,
I am trying to build a hierarchical design using Innovus, but I have a problem with closing the timing.
My design is composed by different clone and master blocks. I partition the design and I do the block level implementation for each master partition. From the block level implementation I generate DEF, LIB and LEF files, along with the netlist (.v file) of each master partition. I manage to fix the timing in each partition. The problem comes when I am trying to close the timing on the top level. I am using the LIB and LEF files to create the layout and do the clock tree synthesis and Routing. Up to the point before I assemble the design everything looks to be ok. After I assemble the design the timing breaks down. One issue that I notice, is that the clock used after assembling the design, when I do the timing analysis, is the ideal clock. I use the update_clock_latencies command to get the actual clock and that is when the timing gets violated.
I have also used the set_propagate_clock command in my constraints when importing the top design. That solved the ideal clock problem (now i am getting propagated clock), but the overall timing violation issue remained. Meaning that before assembling the design everything works as expected and the timing is met. After I assemble the design the timing gets violated.
I am sorry if the question is kind of stupid, my experience is limited. Any help would be greatly appreciated.
Best Regards,
Dimitrios