Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.
How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ?
thank you for your time.