regarding leakage power in lvt cells
hello everybody, can any body please explain why leakage power is more in lvt cells.what is relation between Vt and leakage.inversion can be acheived early if my Vt is less.how it...
View ArticleBoundary timing optimization
How to do boundary optimization in soc encounter.By following we can fix boundary timings setClockDomains -fromType input -toType register & setClockDomains -fromType register -toType outputBut,...
View ArticleROM from cells.
Hi,I’m working with the technology which doesn’t have ROM. So I need to implement it by tie cells or any other way. Does Encounter have a solution for such a case, or may be somebody has an experience...
View ArticleELC Simulation failed with status 512
I am trying to create a standard cell library with transistor level model written in verilog A. I am getting the following output -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-...
View ArticleRegarding skew from clock Report
Hi all,,, Nr. of Subtrees : 118Nr. of Sinks : 18810Nr. of Buffer : 3231Nr. of Level (including gates) : 23Root Rise Input Tran : 100(ps)Root...
View ArticlePlacement density
What are the implications of placement density?How to determine the optimum placement density for a design?
View Articleclock ECO flow
During ECO process, i have to add a few flops. However i don't know which level of the clock tree these flops have to be connected? Is there a way by which the tool automatically detects/connects...
View ArticleHow to add tap cells
Hi,I want to add tap cells manually around a placement blockage.So can any 1 help me out how to do thisLike how to call in the tap cells within the design and place them like a macro around the...
View ArticlecreatePinGroup SEGV Error
Hi All, Here is a stack trace situation in encounter. Even in 9.1 . Any design can be used to replicate this crash. createPinGroup nLeft -pin {ILEAD_OFF[0] ILEAD_OFF[1]} createPinGuide -edge 1...
View ArticleList of paths for a particular endpoint
Hi,For writting a script, I need to find all the paths that a connected to an endpoint of a particular flop with slack values.I have three flops( ff3 , ff31 , ff32) communicating with ff4. I need to...
View ArticleDifference between checkDrc and verify geometry in EDI
Hi, Can anyone tell me what is the diff between checkDrc and verify geometry.Why we are getting too many violations while using checkDrc command. why should we use verify geometry instud of checkDrc...
View Articleregarding differnt types of modes
what is differnce in following modes:1.scan shift mode2.scan capture mode3.rambist mode4.funtional mode5.test modeple any one explain me
View ArticleQuestion of cell placement in P&R (SOC encounter)
Hi,When I try to place standard cells into the floorplan, I notice that the cells are not averagely distributed, no matter how I set the utilization percentage. Please check out the attacked picture. I...
View ArticleHow to find dont use cells in thedesign using dbGet command
Hi All,as i now we can find the don't use cells in the design using get_attribute command. But i want to find don't use cells in the design using dbGet commands. Thank youPhanendra
View Articleend of line problems
I have meet lots of "end of line problems". They are all about the distance of the lines for the standard cells.I also attached one example.How do I solve this kind of problems?Thanks.
View ArticleIntel Xeon E5-2690
Are any of the EDI algorithms / stages optimized for the new Intel Xeon cpu's ?For placeDesign + optDesign -preCTS I am only seeing a 7% runtime improvement.E5-2690 14hours vs X5680 15hours...
View Articleshort circuit problems in P & R
I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.Then there are some short circuit problems when some signals pass through the vias. Is...
View ArticleOn Chip Variation OCV
Hi all,Can some one explain What is OCV ? I am confused that, --> applying derates is what OCV is ? or --> using two different libs for same (setup/hold) analysis for launch and capture is OCV...
View ArticleA problem in ELC (Encounter Library Characterizer)
Hi, I am characterizing standard cells, but I have the following problem. When I run db_spice, elc says "[WARNING(db_spice)]No spice simulation to do, please check the cell/process list for any error",...
View ArticleConstraining cell placement
I am looking for commands in Encounter that will group cells together in close proximity, but I can't seem to find them. The commands would be similar to magnet_placement, create_rp_group, and...
View Article