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= and => conflict, did IEEE spec resolve that?
Hello,According to ieee.1364 9.2.1:“A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1)”and 9.2.2:“The...
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Using Encounter/ Innovus , need parasitic information layer wise information.
Pretty much the title, I have a requirement of getting the layer wise parasitic information. Is there a utility or an option in the gui that allows me to get extraction for specific nets or specific...
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addStripe command for multiple power domains
Hello,I have multiple (6) power domains in my design. I am placing stripes using the addStripe command but every time I am ending up with a design in which the rails are extending outside the selected...
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Hierarchical Design using characterized blocks timing issues
Hello,I am trying to build a hierarchical design using Innovus, but I have a problem with closing the timing.My design is composed by different clone and master blocks. I partition the design and I do...
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Dangling wires/extra net length using -sroute command
Hello,I am using multiple power domains in my design and while doing the routing of power structures (using the -sroute command), I see that the VDD_CORE1 wire (in my case) always extends by a small...
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Innovus CTS for a range of clock
Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.How can I configure...
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Encounter's "common timing library"
From all the documentation that I see, it looks like "common timing library" in encounter's "import design" menu should point to the typical case library. Similarly to how the "max" and "min" libraries...
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Hierarchical Top-Down CPF flow
Hi,Using the hierarchical partitioning flow, I want to create an individual power domain for each partition, which can be turned off. I've been reading the Innovus user guide "Multiple Supply Voltage...
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Innovus do not perform antenna rule properly
We know, through jogging higher metal layer antenna rules violation could be solved (most of the case).When I import my gds , there are some antenna violation which could be solved through jogging...
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How do I get HAL to check on basic VHDL codes for synthesizability?
I am using this function however I am unable to check basic errors like missing signal in sensitivity list.What can I do now? hal -V93 -GUI -nowarn MAXLEN -nowarn CTLCHR -nowarn IDLENG -nowarn NUMSUF...
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Cadence Encounter
Hello,Is there a way to extract the placement information of the gates (like in X Y coordinates)in soc Encounter?I would use this information to know the neighboring pair of gates throughout my...
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How to define sdc file description for internally generated clock ?
In my design, I have a clock generation block which generate main clock pulse ( no external clock reference is used like PLL ) . I'm facing problem defining sdc clock description.I've tried;...
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How to save global routing output (ie. guide for Detailed Routing)?
Hi,I want to execute global routing and export the global routing output in a file, probably a .guide file such as the ones in the benchmarks of ISPD 2018 Contest...
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how to have CLASS BUMP statement under the PORT statement in LEF ?
My design block macro have a pin to be connected to bump directly at the top level ( I wantthe P&R person to place a bump at the center of that pin). According to EDI system user guide,the PORT...
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Real Nets not Annotated
I am having a lot of difficulty with a flip chip Area IO design. In the design, the IO cell with pin PAD is connected to a BUMP using fcRoute (wide top level metal, low resistance). When I run...
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Issues with Verify Connectivity on Soc Encounter
Hello,I have somme issues with Veriffy Connectivity on Soc Encounter. Actually when I run veriffy connectivity I have somme violations on pad rings (ring_VDD and ring_GND) as Open.I do the connect...
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Issues with nanoroute Soc Encounter
Hello,when I am doing nanoroute with soc encounter, i have my I/O nets not routed to the PADs Pins but when I do veriffy connectivity, I don't have violations in these I/O nets.When I check the wires...
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Innovus: import hard-macros placement from open-access layout view with some...
Dear all,I'm trying to benefit from OA interoperability between Innovus and Cadence IC (Virtuoso) environments for a digital-on-top mixed-signal design. In short, during floorplan I would like to...
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How to simulate a fully differential input/output buffer .ibis model in...
Hello,Could you please layout the details, how to simulate a fully differential output buffer(Tx) and fully differential input buffer(Rx) ibis model in Virtuoso?!The ibis buffer from analogLib is not...
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Innovus: Does not detect Inverters in library
Dear all,I'm using Innovus to P&R a design consisting of custom made cells. The cells have been characterized and compiled into a .lib file using Synopsys SiliconSmart.Everything works as expected,...
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