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Shorts over Macro
hi,we are observing shorts over macro edges due to high pin density. but we have are observing channels which we gave is not fully utilized.is there any settings to to fix shorts over macros with high...
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Issue with hold time when migrating from Encounter to Innovus
Hello, I am trying to migrate my digital synthesis flow from Encounter (v12.00-p002_1) to Innovus (v19.14-s105_1) by updating the script that used to work with Encounter. After replacing the commands...
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Issue when exporting the Innovus layout to Virtuoso
Hi all,I am doing some digital implemtation staff. I used Innovus to do PnR, and export the layout using GDS format to virtuoso. Problem: All the label layers imported to Virtuoso appear to be drawing...
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Extracting LEF Hierarchically in Innovus
Hello,I am currently using Innovus to build a hierarchical design where the levels of hierarchy can range from 2 to 6/7. I'm having some issues right now getting the -extractBlockObs flag to work for...
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Use separate power for handful of std cells and one macro
Hey everyone,First off, any help would be greatly appreciated and thank you to anyone who does respond.I have a large design that uses a single VDD and VSS throughout, except for a single small portion...
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INNOVUS - write_lef_abstract -design_boundary Option
Hello,I am seeing:"**ERROR: (IMPLF-1000): Illegal value found for -design_boundary option."when trying to use the -design_boundary flag with write_lef_abstract. The man page simply says to use a point...
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Cadence Voltus - multiple power pins -setting name and voltages
Hi, In my design I have two power pins: VDD and VDD1 and two ground pins: VSS and VSS1.While running static power how can i set the names and voltages of the different power and ground pins??Thanks...
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Innovus DefIn and ecoDefIn handling of metal shapes differently.
Hello Team,Tool: Innovus 19.10 and 19.12Running FEF PostMask and can successfully complete an ECO change, except for one tedious task: fixing or removing little Special Route metals labeled at...
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using globalNetConnect to define a signal as a power source to part of a design
I have no issue connecting my VDD and VSS (pwr/gnd) to my macros and std cells, but in this current iteration of my design, I have a SRAM and 45 std cells that I need to connect to a different power...
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Max_tran violation not resolved in INNOVUS
Hi,there is a way to know why INNOVUS optDesign -postroure is not able to solve a max_tran violation ?
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DEVICE MODEL INTERFACE
Hi everyone,I have a very simple RC circuit made on Simulink and I would like to import it on PSpice so I should use the DMI to interface Simulink and PSpice. I used this link as a guide...
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CCOpt Insertion Delay
Hello,I am building a clock tree with multiple generated clocks and would like to define different insertion delay for each skew group for an optimized balancing, how is this possible using...
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Import design innovus
Dear all,I have saved a synthesized design in genus using the write_design -basename basename -innovus and when I import the design into innovus I see that it has not connected some output ports. When...
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AoT Virtuoso Digital Implementation License Error
Hi,I am following a RAK Analog on Top (AoT) Mixed Signal Design Flow Using Virtuoso Analog and Innovus Digital Platforms: Rapid Adoption Kit (RAK) and the licenses required are: Virtuoso GXL, Innovus...
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Overriding the max_transition parameter from .lib file in Innovus
Hi All,How can I set a proper value for max_transition during PnR in Innovus ? Even if I use following commands (during MMMC analysis / OCV mode), Innovus seems to take the max_transition from the fast...
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Symbol loading error
Hello everyone. I tried to add a symbol of a battery holder. I had downloaded the footprint and STEP model. I've noticed that pins in that footprint were defined as mechanical, so I had to replace them...
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Clock tree synthesis error using innovus
Hi All,When I using the innovus to synthesis the clock tree using the following command:create_ccopt_clock_tree_spec -filename ccopt.specsource ccopt.specccopt_design -ctsI found the errors shown...
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What's the advantage for declaration different clock domain in Genus
Hello,Recently I find that in Genus is supporting function of declaration different clocking domains. Instead using clock groups and than add them as asynchronous, domains seems to ignore all...
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Joules RTL power analysis can not recognize defined parameter
I used RTL to analysis power with Joules but there was an error occur when i generated db file.The error information: Invalid Verilog syntax is parsed, or unsupported Verilog syntax is encountered.I...
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Direction of VDD/VSS (inout vs input)
What is the reason that power/ground ports that are added in the physical implementation flow have direction "inout" instead of "input"? Is there a way to force them to be "input" instead without...
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