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Can Voltus do an IR drop analysis on a negative supply?
I have been using Voltus to do IR drop analysis but I got caught on one signal. It is negative. When I use:set_pg_nets -net negsupply -voltage -5 -threshold -4.5 -package_net_name NEGSUP -forceVoltus...
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How do I setup a student License?
I recently received a student version or OrCad, which I was able to download and install without trouble. However, I do not know how to setup my license.I received the license file in an email. The...
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Verilog Code to Custom IC Layout generation
Hello everyone,I am Vinay and I am currently developing some digital circuits for my chip design for my master's thesis at University at Buffalo.I am fairly very new to Verilog and I don't seem to...
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Which algorithm is used in Modus ATPG?
According to the book Electronic Design Automation For Integrated Circuits Handbook there are mutiple algorithms available. Quote from book: "One of the first complete ATPG algorithms is the...
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About modus design constraints
Hi! In my design, there is an one hold violation on scan path, test data is corrupted during scan cycles (when i run verilog simulation of test vectors). I created constraint 'falsepath' to 'TI' input...
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unable to follow through the vdi flow.
hope someone could shed light on it.the log file is herehttps://gitee.com/chaujohnthan/temporal/blob/master/VDIVceToInn.logv
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Typical delay values for reset glitch filter in 28nm.
I found some glitch filter design on the internet but I am unsure of how to set a typical value for the the glitch delay. Assume the clock speed is 800MHz on a die of 3*3mm at 28nm. How should one...
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Quantus Qrc Extraction of a block
I have completed physical design of a block in innovus. I want to extract rc of that block using quantus . It will be very helpful if you give step by step procedure and command to run quantus to...
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In power pins unconnected
Hi,When I import the top level Verilog file generated by Genus into Virtuoso, the power pins are left unconnected. I tried different configurations in "Global Net Options" tab. However, nothing...
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Interaction between Innovus and Virtuoso through OA database
Hello,I created a floorplan view in Virtuoso ( it contains pins and blockages). I am trying to run PnR in Innovus for floorplan created in Virtuoso. I used set vars(oa_fp) "Library_name cell_name...
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How to write Innovus Gui command to a cmd/log file?
HI, I have been using the Innovus GUI commands for several things and wonder if those command can be written to a log or cmd file so I can use it in my flow script? Is there such options that we can...
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How to place pins inside of the edge in Innovus
Hi,I am doing layout for a mixed-signal circuit in Innovus. I want to create a digital donut style of layout (i.e. put analog circuit in the middle, and circle analog part with digital circuits).To do...
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checkRoute or VerifyConnectivity
Hello Everyone,I was finishing the layout via Innovus and ran verifyConnectivity followed by checkRoute.verifyConnectivity was okay and it showed no errors and no warnings, whereas checkRoute showed...
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Viewing RTL Code Coverage reports with XCELIUM
Hi,There was tool available with INCISIV called imc to view the coverage reports.The question is: How can we view the code coverage reports generated with XCELIUM? I think imc is not available with...
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Power Grid Design
Hi, Given the power consumption of a design, how can we go about designing the power grid for the design in Innovus? Is there a method to compute the minimum width for the rings and stripes, via nos,...
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Power grid design Innovus
Hi, Given the power consumption of a design, how can we go about designing the power grid for the design in Innovus? Is there a method to compute the minimum width for the rings and stripes, via nos,...
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How to close design in Innovus or remove design from Innovus (remains on disk)?
One way is to exit the tool. I tried a few things but couldn't find such basic command.
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Modus IC Test DLI algorithm
Hello IC Designs.I want some information about the DLI (Defect Location Identification) algorithm based in Modus IC Test.I have some difficults to understand the branching for DLI.Standard cell ->...
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Fixing Process Antenna Violations using Nanoroute
Hi,I am getting 47 Process Antenna Violations after routing my design, all these violations are on intermediate layers. When I try to run Nanoroute(modes mentioned below), it does not adds any antenna...
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Innovus Foundation Flow : DRC violation short with cellblockage
Hi,I am trying to place and rout a simple test design using Innovus foundation flow.But at the end of the flow, I get a short between nets and cell blockage.I tried to increase the designed area to a...
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